公开(公告)号：US20070299991A1

公开(公告)日：2007-12-27

申请号：US11485750

申请日：2006-07-13

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A DMA module is described which, in order to read or write a memory location within a DMA process, accesses by a reading operation a memory location of an addressable memory (5) identified by a first address (46) in order to read there at least one second address (52); which advances the second address (52) to an adjacent memory location, and implements a write access or read access at a memory location identified by the second address (52); and which finally stores the second address at the memory location identified by the first address (46).

摘要翻译： 描述了DMA模块，为了读取或写入DMA进程内的存储器位置，通过读取操作访问由第一地址（46）标识的可寻址存储器（5）的存储器位置，以便在那里读取 至少一秒地址（52）; 其将所述第二地址（52）前进到相邻存储器位置，并且在由所述第二地址（52）标识的存储器位置处实现写访问或读访问。 并且其最终将第二地址存储在由第一地址（46）标识的存储位置处。

公开(公告)号：US4882610A

公开(公告)日：1989-11-21

申请号：US254071

申请日：1988-10-06

申请人： Ulrich Theus ,  Burkhard Giebel

发明人： Ulrich Theus ,  Burkhard Giebel

IPC分类号： H01L29/78 ,  H01L27/02

CPC分类号： H01L27/0251 ,  H01L2924/0002

摘要： In this protective arrangement, a resistor between a pad (p) and a transistor to be protected is implemented with an expansion region (e) which lies completely below the pad (p) and extends beyond the latter along the entire circumference of the pad. An elongate region (z) extends along the circumference of the expansion region (e) and is connected to circuit ground via an interconnection track (b). The connection between the elongate region (z) and the interconnection track (b) has a low resistance.

摘要翻译： 在该保护装置中，垫（p）和被保护晶体管之间的电阻器具有完全位于焊盘（p）下方的扩展区域（e），并且沿着焊盘的整个圆周延伸超出焊盘（p）。 细长区域（z）沿着扩展区域（e）的圆周延伸并且经由互连轨道（b）连接到电路接地。 细长区域（z）和互连轨道（b）之间的连接具有低电阻。

公开(公告)号：US4742253A

公开(公告)日：1988-05-03

申请号：US460957

申请日：1983-01-25

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： H01L21/822 ,  G11C7/06 ,  G11C11/417 ,  G11C17/18 ,  H01L21/66 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H03K5/08 ,  H03K17/687

CPC分类号： G11C7/067 ,  G11C11/417

摘要： The circuit merely comprises three transistors, namely one transfer transistor (t) arranged between the input (e) and the output (a), a load transistor (l) connected as a resistor, and a clamping transistor (k), with both of the latter connecting the output (a) to the source of operating voltage (U). The interconnected gates of both the clamping and the transfer transistor (k, t) are connected to a source of reference voltage (Ur). If these two transistors (k, t) are of the depletion type, the two gates thereof may be connected to the zero point of the circuit. The circuit is particularly quick and simple.

摘要翻译： 电路仅包括三个晶体管，即布置在输入（e）和输出（a）之间的一个传输晶体管（t），作为电阻器连接的负载晶体管（l）和钳位晶体管（k） 后者将输出（a）连接到工作电压源（U）。 钳位和转移晶体管（k，t）的互连栅极连接到参考电压源（Ur）。 如果这两个晶体管（k，t）是耗尽型，则其两个栅极可以连接到电路的零点。 电路特别快捷简单。

公开(公告)号：US5608346A

公开(公告)日：1997-03-04

申请号：US491500

申请日：1995-06-16

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： H03K19/00 ,  H03K17/16

CPC分类号： H03K19/0013

摘要： A MOS driver circuit has a first output transistor and a second output transistor which are driven in push-pull into a conducting state by a first driver stage having first high impedance and first low impedance elements and a second driver stage having second high impedance and second low impedance elements, respectively. The high impedance driver elements drive the output transistors into a conducting or nonconducting state and the low impedance driver elements hold the output transistors in the nonconducting state. The junction of the output transistors can be connected to a load. A holding stage for each driver stage is cross coupled to a high impedance driver element of one output transistor and the low impedance driver element of the other output transistor, so as to drive one output transistor in the conducting state while holding the other output transistor in a nonconducting state. As a result, shunt currents between the output transistors are avoided even in the presence of output noise.

摘要翻译： MOS驱动器电路具有第一输出晶体管和第二输出晶体管，所述第一输出晶体管和第二输出晶体管通过具有第一高阻抗和第一低阻抗元件的第一驱动级被推挽驱动而导通状态，以及具有第二高阻抗和第二高阻抗元件的第二驱动级 低阻抗元件。 高阻抗驱动器元件将输出晶体管驱动成导通或不导通状态，并且低阻抗驱动器元件将输出晶体管保持在非导通状态。 输出晶体管的结可以连接到负载。 每个驱动级的保持级与一个输出晶体管的高阻抗驱动器元件和另一个输出晶体管的低阻抗驱动元件交叉耦合，以便将一个输出晶体管驱动在导通状态，同时将另一个输出晶体管保持在 非导体状态。 结果，即使在存在输出噪声的情况下也避免了输出晶体管之间的分流电流。

公开(公告)号：US4502131A

公开(公告)日：1985-02-26

申请号：US530528

申请日：1983-09-09

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G11C29/00 ,  G11C29/34

CPC分类号： G11C29/34

摘要： An electrically programmable memory includes a test circuit usable for detection of interaction between adjacent memory cells by easily permitting a checkerboard-pattern to be programmed into the memory.

摘要翻译： 电可编程存储器包括可用于通过容易地将棋盘图形编程到存储器中来检测相邻存储器单元之间的相互作用的测试电路。

公开(公告)号：US4458338A

公开(公告)日：1984-07-03

申请号：US290514

申请日：1981-08-06

申请人： Burkhard Giebel ,  Hans Moormann ,  Lothar Schrader

发明人： Burkhard Giebel ,  Hans Moormann ,  Lothar Schrader

IPC分类号： G01R31/26 ,  G06F12/16 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C7/00

CPC分类号： G11C29/46 ,  G11C29/34

摘要： Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of the semiconductor memory with the exception of one selected word line are at a low level. The circuit arrangement also has an inactive power-down mode of operation, wherein all word lines at a high level. Both of the modes of operation are represented by a signal having a first level for the active mode of operation and a second level for the inactive mode of operation. The circuit arrangement further includes a single circuit in the semiconductor memory switchable via a first signal indicating the operating mode for the memory cell test, wherein all of the word lines are addressed by a voltage corresponding to the programming voltage, as a function of a single second signal fed into the semiconductor memory from the outside, from the level indicating the active mode of operation to the level indicating the inactive mode of operation, so that all the word lines can be switched simultaneously to the level required for programming.

摘要翻译： 用于检查可编程MOS集成半导体存储器，特别是浮栅型非易失性半导体存储器的存储单元的电路布置具有有效的编程和读操作模式，其中半导体存储器的所有字线除了一个选定的 字线处于低水平。 电路装置还具有无效的掉电操作模式，其中所有字线处于高电平。 这两种操作模式由具有用于主动操作模式的第一级的信号和用于非活动操作模式的第二级来表示。 该电路装置还包括半导体存储器中的单个电路，其经由指示存储器单元测试的工作模式的第一信号可转换，其中所有字线由与编程电压相对应的电压作为单个电路的函数 第二信号从外部馈送到半导体存储器，从指示活动操作模式的电平到指示不活动操作模式的电平，使得所有字线可以同时切换到编程所需的电平。

公开(公告)号：US4388541A

公开(公告)日：1983-06-14

申请号：US171342

申请日：1980-07-23

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G11C17/00 ,  G11C11/4063 ,  G11C16/26 ,  G11C17/18 ,  H03K19/017 ,  H03K19/0175 ,  H03K5/12 ,  H03K19/094

CPC分类号： H03K19/01721 ,  G11C11/4063 ,  G11C16/26

摘要： Circuit having MOS-transistors for the rapid evaluation of the logic state of a sampling node, including a circuit input connected to the sampling node, a circuit output, a supply voltage source, an inverter being connected to the circuit input and having an output, a first transistor being connected between the circuit input and the circuit output and having a gate connected to the output of the inverter, a second transistor being connected between the supply voltage source and the circuit output and having a gate connected to the output of the inverter, and a third transistor shunted across the second transistor as a load resistor.

摘要翻译： 具有用于快速评估采样节点的逻辑状态的MOS晶体管的电路，包括连接到采样节点的电路输入，电路输出，电源电压源，连接到电路输入并具有输出的反相器， 第一晶体管连接在电路输入端和电路输出端之间，并具有连接到反相器的输出端的栅极，第二晶体管连接在电源电压源和电路输出端之间，并具有连接到反相器的输出端的栅极 并且作为负载电阻器将分流在第二晶体管上的第三晶体管分流。

公开(公告)号：US20090153187A1

公开(公告)日：2009-06-18

申请号：US10580780

申请日：2004-11-24

申请人： Reiner Bidenbach ,  Jörg Franke ,  Burkhard Giebel ,  Markus Rogalla

发明人： Reiner Bidenbach ,  Jörg Franke ,  Burkhard Giebel ,  Markus Rogalla

IPC分类号： H03K19/173

CPC分类号： G06F11/24

摘要： The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs.

摘要翻译： 本发明涉及包括单片集成逻辑IC的集成电路和与逻辑IC导电连接的单片集成接口电路。 所述接口电路的电气特性是可编程的。 接口电路的集成密度也低于逻辑IC，并且包括用于监视逻辑IC的监控模块。

公开(公告)号：US5912581A

公开(公告)日：1999-06-15

申请号：US919455

申请日：1997-08-28

申请人： Burkhard Giebel ,  Ulrich Theus

发明人： Burkhard Giebel ,  Ulrich Theus

IPC分类号： H05K9/00 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003 ,  H01L21/82

CPC分类号： H03K19/00346

摘要： Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

摘要翻译： 用于在非屏蔽板网络内可操作的集成电路，特别是单片集成电路的杂散发射减少端子配置，该集成电路被分成具有实质上是射频电流分量的第一子电路和第二子电路，其中 具有基本的低频电流分量，分离也延伸到内部电源线并提供接触焊盘。 第二支路包括连接到电路板网络上的I / O线路的驱动电路。 在接地侧，第一和第二电源电流路径通过低电阻和低电感连接在集成电路内互连以建立接地点。

公开(公告)号：US5451861A

公开(公告)日：1995-09-19

申请号：US131258

申请日：1993-10-01

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： H03K17/12 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K5/12

CPC分类号： H03K17/166 ,  H03K19/00361

摘要： The invention is a method and circuit for improving the settability of the output current (i1) of at least one pad driver (D: D1, D2, . . . Dn) to reduce interfering voltage dips on the supply lines. The pulselike current peaks caused by rapid charging/discharging of high load capacitances (c) are particularly avoided. To this end, the respective output transistor (t1, t1') is operated as a current-controlled element in a first range (b1) of the output voltage (OUR) and as a voltage-controlled element in a second range (b2).

摘要翻译： 本发明是一种用于改善至少一个焊盘驱动器（D：D1，D2 ... Dn）的输出电流（i1）的可稳定性以减少电源线上的干扰电压下降的方法和电路。 特别是避免了由高负载电容（c）的快速充电/放电引起的脉动电流峰值。 为此，相应的输出晶体管（t1，t1'）作为输出电压（OUR）的第一范围（b1）中的电流控制元件和作为第二范围（b2）中的电压控制元件， 。