公开(公告)号：US09785738B1

公开(公告)日：2017-10-10

申请号：US14972809

申请日：2015-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Charles Jay Alpert ,  Zhuo Li ,  Wing Kai Chow ,  Wen-Hao Liu ,  Derong Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.

公开(公告)号：US11868695B1

公开(公告)日：2024-01-09

申请号：US17219730

申请日：2021-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

IPC: G06F30/337 ,  G06F16/22

CPC classification number: G06F30/337 ,  G06F16/22

Abstract: Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.

公开(公告)号：US11188702B1

公开(公告)日：2021-11-30

申请号：US17139617

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Bentian Jiang ,  Natarajan Viswanathan ,  William Robert Reece ,  Zhuo Li

IPC: G06F30/392 ,  G06F30/398 ,  G06F119/18

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

公开(公告)号：US10990721B1

公开(公告)日：2021-04-27

申请号：US16718018

申请日：2019-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/33 ,  G06F30/31 ,  G06F30/398

Abstract: Electronic design automation systems, methods, and media are presented for cell cloning during circuit design. In one embodiment, for a circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree, a delay is identified for each flip-flop element. The flip-flop elements are clustered by delay to generate at least two clusters of flip-flop elements. Elements within the clusters are then grouped by physical characteristics to generate delay groups of flip-flop elements. An updated routing tree is then generated for the circuit design using the first delay group and the second delay group.

公开(公告)号：US10860775B1

公开(公告)日：2020-12-08

申请号：US16384668

申请日：2019-04-15

Applicant: Cadence Design Systems, Inc.

Inventor： Wing-Kai Chow ,  Zhuo Li

IPC: G06F30/30 ,  G06F30/398 ,  G06F30/34 ,  G06F111/04 ,  G06F119/12

Abstract: Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.

公开(公告)号：US10685164B1

公开(公告)日：2020-06-16

申请号：US16239310

申请日：2019-01-03

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

公开(公告)号：US10460063B1

公开(公告)日：2019-10-29

申请号：US15649402

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Gracieli Posser ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

公开(公告)号：US10095824B1

公开(公告)日：2018-10-09

申请号：US15293010

申请日：2016-10-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/00 ,  G06F17/50

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.

公开(公告)号：US11734485B1

公开(公告)日：2023-08-22

申请号：US17314932

申请日：2021-05-07

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Derong Liu ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

公开(公告)号：US11514222B1

公开(公告)日：2022-11-29

申请号：US17207266

申请日：2021-03-19

Applicant: Cadence Design Systems, Inc.

Inventor： Sheng-En David Lin ,  Yi-Xiao Ding ,  Jhih-Rong Gao ,  Zhuo Li

IPC: G06F30/394 ,  G06F111/04 ,  G06F117/10

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.