公开(公告)号：US20130121396A1

公开(公告)日：2013-05-16

申请号：US13293513

申请日：2011-11-10

申请人： Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

发明人： Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC分类号： H04L27/01

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

摘要： A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

摘要翻译： 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

公开(公告)号：US20110310690A1

公开(公告)日：2011-12-22

申请号：US12820712

申请日：2010-06-22

申请人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tien Chun YANG ,  Chih-Chang LIN ,  Yuwen SWEI

发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tien Chun YANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC分类号： G11C5/14

CPC分类号： G11C11/4074 ,  G11C5/147

摘要： A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.

摘要翻译： 电压调节器包括与电压调节器的输出端电耦合的输出级。 输出级包括具有体积和漏极的至少一个晶体管。 至少一个背偏置电路与所述至少一个晶体管的主体电耦合。 至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

公开(公告)号：US20130342247A1

公开(公告)日：2013-12-26

申请号：US13530136

申请日：2012-06-22

申请人： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

发明人： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

IPC分类号： H03L7/08

CPC分类号： H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

摘要翻译： 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20120230457A1

公开(公告)日：2012-09-13

申请号：US13045788

申请日：2011-03-11

申请人： Chan-Hong CHERN ,  Chih-Chang LIN ,  Ming-Chieh HUANG ,  Fu-Lung HSUEH

发明人： Chan-Hong CHERN ,  Chih-Chang LIN ,  Ming-Chieh HUANG ,  Fu-Lung HSUEH

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/113 ,  H04L7/0337

摘要： A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

摘要翻译： 时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。 延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。 电荷泵配置为控制LCVCO。 相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

公开(公告)号：US20140266114A1

公开(公告)日：2014-09-18

申请号：US14291426

申请日：2014-05-30

申请人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

发明人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC分类号： H02M3/158

CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

摘要： A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

摘要翻译： 电压调节器电路包括具有反相输入和非反相输入的放大器。 放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。 电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点，第一功率节点，第二功率节点和驱动器。 驱动器耦合在第一功率节点和输出节点之间。 具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。 放大器外部的偏置电路向第一晶体管的栅极提供偏置信号，该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。

公开(公告)号：US20130346811A1

公开(公告)日：2013-12-26

申请号：US13528877

申请日：2012-06-21

申请人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

IPC分类号： G06F1/04 ,  G06F11/00

CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

公开(公告)号：US20130141170A1

公开(公告)日：2013-06-06

申请号：US13312228

申请日：2011-12-06

申请人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

发明人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC分类号： H03F3/68

CPC分类号： H03F3/68 ,  H03F1/42 ,  H03F3/191 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/36 ,  H03F2200/405 ,  H03F2203/45638 ,  H03F2203/45702

摘要： A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

摘要翻译： 共享用于具有至少两级的放大器的感应峰化的电感器的方法包括计算用于感应峰值的至少两级的单级的单级电感，以便具有稳定的脉冲响应。 通过将单级电感除以至少两级的多个级来计算感应峰值的共享电感。 具有共享电感的至少两个电感器在用于感应峰化的至少两个级中共享。

公开(公告)号：US20100253303A1

公开(公告)日：2010-10-07

申请号：US12750260

申请日：2010-03-30

申请人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

发明人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC分类号： G05F1/10

CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

摘要翻译： 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。

公开(公告)号：US20110267107A1

公开(公告)日：2011-11-03

申请号：US12768899

申请日：2010-04-28

申请人： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Bryan SHEFFIELD ,  Chih-Chang LIN

发明人： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Bryan SHEFFIELD ,  Chih-Chang LIN

IPC分类号： H03K19/094 ,  H03K19/096

CPC分类号： H03K19/01855 ,  H03K3/012 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H03K19/0963

摘要： A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.

摘要翻译： 电路包括逻辑门驱动器的操作PMOS晶体管。 控制电路被配置为在待机模式期间关闭操作PMOS晶体管。 电路还包括耦合到输出节点的牺牲PMOS晶体管。 操作PMOS晶体管耦合到输出节点。 牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。

公开(公告)号：US20120013374A1

公开(公告)日：2012-01-19

申请号：US12835130

申请日：2010-07-13

申请人： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

发明人： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/081 ,  H03L7/087

摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

摘要翻译： 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。