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    Computer architecture and software cells for broadband networks
    11.
    发明授权
    Computer architecture and software cells for broadband networks 有权
    宽带网络的计算机架构和软件单元

    公开(公告)号：US07720982B2

    公开(公告)日：2010-05-18

    申请号：US11716845

    申请日：2007-03-12

    申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

    发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

    IPC分类号： G06F15/16

    CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

    Multi-Chip Module With Third Dimension Interconnect
    12.
    发明申请
    Multi-Chip Module With Third Dimension Interconnect 审中-公开
    具有三维互连的多芯片模块

    公开(公告)号：US20080256275A1

    公开(公告)日：2008-10-16

    申请号：US12049323

    申请日：2008-03-15

    申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    IPC分类号： G06F13/00

    CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    Method and apparatus for coherent memory structure of heterogeneous processor systems
    14.
    发明授权
    Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
    异构处理器系统的相干存储器结构的方法和装置

    公开(公告)号：US07093080B2

    公开(公告)日：2006-08-15

    申请号：US10682386

    申请日：2003-10-09

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0835

    摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

    摘要翻译： 公开了与非均匀处理单元结合操作的一致的缓存系统。 一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。 需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。 每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

    System and method for a configurable interface controller
    15.
    发明授权
    System and method for a configurable interface controller 有权
    可配置接口控制器的系统和方法

    公开(公告)号：US08108564B2

    公开(公告)日：2012-01-31

    申请号：US10697903

    申请日：2003-10-30

    申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    IPC分类号： G06F3/00

    CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

    摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

    摘要翻译： 灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。 灵活的I / O接口以特定组件确定的速率从组件接收数据。 然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。 因此，保持与各个I / O控制器的接口。 灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。 在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

    Non-Homogeneous Multi-Processor System With Shared Memory
    17.
    发明申请
    Non-Homogeneous Multi-Processor System With Shared Memory 审中-公开
    具有共享内存的非均匀多处理器系统

    公开(公告)号：US20080162877A1

    公开(公告)日：2008-07-03

    申请号：US12049324

    申请日：2008-03-15

    申请人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    发明人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： H04L63/168 ,  H04L67/10

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    System and method for flexible multiple protocols
    18.
    发明授权
    System and method for flexible multiple protocols 有权
    灵活多协议的系统和方法

    公开(公告)号：US07389363B2

    公开(公告)日：2008-06-17

    申请号：US11050022

    申请日：2005-02-03

    申请人： Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

    发明人： Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

    IPC分类号： G06F3/00

    CPC分类号： G06F13/385

    摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.

    摘要翻译： 介绍了灵活多协议的系统和方法。 可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。 在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。 在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。