公开(公告)号：US08987098B2

公开(公告)日：2015-03-24

申请号：US13527259

申请日：2012-06-19

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L21/336 ,  H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/11565

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

公开(公告)号：US08889509B2

公开(公告)日：2014-11-18

申请号：US13210202

申请日：2011-08-15

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L21/336 ,  H01L29/792 ,  H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract translation: 一种存储单元，包括：具有表面的半导体衬底，源极区和漏极区设置在衬底的表面下方并被沟道区分开; 设置在沟道区域上方的具有大于3纳米的有效氧化物厚度的隧道势垒介电结构; 导电层，设置在隧道势垒电介质结构之上并在沟道区之上; 电荷捕获结构，设置在导电层之上并在沟道区上方; 位于所述电荷俘获结构上方且位于所述沟道区上方的顶部电介质结构; 以及设置在顶部电介质结构之上和沟道区上方的顶部导电层以及其制造方法和制造方法。

公开(公告)号：US08759899B1

公开(公告)日：2014-06-24

申请号：US13739914

申请日：2013-01-11

Applicant: Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC: H01L29/788

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

Abstract: An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

Abstract translation: 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20130175598A1

公开(公告)日：2013-07-11

申请号：US13347331

申请日：2012-01-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/792 ,  H01L21/8239

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。

公开(公告)号：US08482052B2

公开(公告)日：2013-07-09

申请号：US12056489

申请日：2008-03-27

Applicant: Hang-Ting Lue ,  Erh-Kun Lai

Inventor： Hang-Ting Lue ,  Erh-Kun Lai

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

Abstract: Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.

Abstract translation: 薄膜晶体管存储单元是可堆叠的，并且采用无结构的NAND配置的带隙工程隧道层，其可以排列成3D阵列。 所述存储单元具有在绝缘层上形成的半导体条中的沟道区，设置在所述沟道区上方的隧道电介质结构，所述隧道电介质结构具有多层结构，所述多层结构包括至少一层具有低于空穴穿透势垒高度的层。 在与沟道区域的界面处，设置在隧道介电结构上方的电荷存储层，设置在电荷存储层上方的绝缘层和设置在绝缘层上方的栅电极。

公开(公告)号：US08363476B2

公开(公告)日：2013-01-29

申请号：US13009464

申请日：2011-01-19

Applicant: Hang-Ting Lue ,  Shih-Hung Chen

Inventor： Hang-Ting Lue ,  Shih-Hung Chen

IPC: G11C16/00

CPC classification number: H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

Abstract translation: 提供了一种存储器件，其制造方法和操作方法。 存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。 堆叠结构设置在基板上。 每个堆叠结构包括串选择线，字线，接地选择线和绝缘线。 串选择线，字线和接地选择线通过绝缘线彼此分离。 通道元件设置在堆叠结构之间。 电介质元件设置在通道元件和堆叠结构之间。 源元件设置在基板的上表面和通道元件的下表面之间。 位线设置在通道元件的上表面上。

公开(公告)号：US08343840B2

公开(公告)日：2013-01-01

申请号：US12763006

申请日：2010-04-19

Applicant: Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

Inventor： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC: H01L21/336 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

Abstract: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Abstract translation: 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US08324681B2

公开(公告)日：2012-12-04

申请号：US13162386

申请日：2011-06-16

Applicant: Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

Inventor： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/792

Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Abstract translation: 堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。 位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。 该器件可以配置为NAND操作。

公开(公告)号：US20120220111A1

公开(公告)日：2012-08-30

申请号：US13463264

申请日：2012-05-03

Applicant: Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

Inventor： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

IPC: H01L21/04

CPC classification number: H01L29/665 ,  G11C16/0408 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

Abstract translation: 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

公开(公告)号：US08252654B2

公开(公告)日：2012-08-28

申请号：US12942312

申请日：2010-11-09

Applicant: Tzu-Hsuan Hsu ,  Hang-Ting Lue

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66833 ,  H01L29/792

Abstract: In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.

Abstract translation: 在存储单元的制造方法中，设置有基板。 在基板的表面附近形成具有第一导电类型的掺杂区域。 去除衬底的一部分以在衬底中限定多个鳍结构。 在翅片结构之间形成多个隔离结构。 隔离结构的表面低于翅片结构的表面。 栅极结构形成在衬底上并跨越翅片结构。 栅极结构包括跨过鳍结构的栅极和位于鳍结构和栅极之间的电荷存储结构。 源极/漏极区域由栅极结构暴露的鳍状结构中的第二导电类型形成，并且第一导电类型不同于第二导电类型。