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79 条记录 (耗时 0.042 秒)

    On-chip impedance matching circuit
    11.
    发明授权
    On-chip impedance matching circuit 有权
    片内阻抗匹配电路

    公开(公告)号：US06798237B1

    公开(公告)日：2004-09-28

    申请号：US10044365

    申请日：2002-01-11

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278

    摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.

    摘要翻译： 提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。 本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。 本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。 片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。 阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。

    Input-output circuit and method of improving input-output signals
    14.
    发明授权
    Input-output circuit and method of improving input-output signals 有权
    输入输出电路及改善输入输出信号的方法

    公开(公告)号：US08610462B1

    公开(公告)日：2013-12-17

    申请号：US13332730

    申请日：2011-12-21

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

    IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03K3/00 ,  H03B1/00

    CPC分类号： H03K3/356113

    摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

    摘要翻译： 公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。 具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。 电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。 当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

    Differential output with low output skew
    15.
    发明授权
    Differential output with low output skew 失效
    差分输出具有低输出偏移

    公开(公告)号：US07551014B1

    公开(公告)日：2009-06-23

    申请号：US11670109

    申请日：2007-02-01

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

    IPC分类号： G06F7/44

    CPC分类号： H04L25/0272

    摘要： Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.

    摘要翻译： 电路和方法提供单端和差分信号。 单端驱动器用于例如降低引脚电容。 输出单元使用诸如分相器的反相电路从相同的输出信号导出差分信号，并在输出引脚之间的差分信号之间提供低偏差。 选择电路用于在单端和差分输出之间进行选择。

    Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit
    19.
    发明授权
    Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit 有权
    用于精确采样输入到集成电路的高频数据信号的技术和电路

    公开(公告)号：US06292116B1

    公开(公告)日：2001-09-18

    申请号：US09571766

    申请日：2000-05-16

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  In Whan Kim ,  Wayne Yeung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  In Whan Kim ,  Wayne Yeung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

    IPC分类号： H03M900

    CPC分类号： H03K19/1774 ,  H03K19/17744 ,  H03M9/00

    摘要： Techniques and circuitry are provided to handle high frequency input data. The techniques and circuitry take a high-frequency serial input data stream and covert it into parallel form for handling within the integrated circuit. The circuitry ensures the high frequency data is strobed properly by accounting for skew between the high frequency data input and clock input. In an implementation, multiple clock strobes are generated having the same frequency but different phase. A predetermined series of bits is input to the high frequency input into the circuitry for training. One of the multiple clock strobes is selected based on which one correctly determines the bits in the predetermined input data stream. This clock strobe is selected to strobe the high frequency data input for the integrated circuit. In an embodiment, the high frequency data input is an LVDS input of a programmable logic integrated circuit.

    摘要翻译： 提供技术和电路来处理高频输入数据。 技术和电路采用高频串行输入数据流，并将其隐藏为并行形式，用于集成电路内的处理。 该电路通过考虑高频数据输入和时钟输入之间的偏斜，确保高频数据正确选通。 在一个实现中，产生具有相同频率但相位相差的多个时钟选通。 将预定的一系列比特输入到用于训练的电路中的高频输入。 基于哪个正确地确定预定输入数据流中的比特来选择多个时钟选通中的一个。 选择该时钟选通脉冲以选通集成电路的高频数据输入。 在一个实施例中，高频数据输入是可编程逻辑集成电路的LVDS输入。