公开(公告)号：US20080018350A1

公开(公告)日：2008-01-24

申请号：US11525581

申请日：2006-09-22

申请人： Clinton Chao ,  Chih-Hsien Chang ,  John C.Y. Chiang ,  Mark Shane Peng ,  Hua-Shu Wu ,  Kim Chen ,  Wen-Hung Wu ,  Tjandra Winada Karta

发明人： Clinton Chao ,  Chih-Hsien Chang ,  John C.Y. Chiang ,  Mark Shane Peng ,  Hua-Shu Wu ,  Kim Chen ,  Wen-Hung Wu ,  Tjandra Winada Karta

IPC分类号： G01R31/02

CPC分类号： G01R1/07378

摘要： An interposer for converting pitches includes an interconnect structure over the semiconductor substrate, an active circuit formed on the semiconductor substrate, wherein the active circuit is electrically connected to the interconnect structure, a first plurality of pads with a first pitch over the interconnect structure, a second plurality of pads underlying the semiconductor substrate, and a plurality of through-substrate vias in the semiconductor substrate, wherein the first and the second plurality of pads are interconnected through the plurality of through-substrate vias.

摘要翻译： 用于转换间距的插入件包括半导体衬底上的互连结构，形成在半导体衬底上的有源电路，其中有源电路电连接到互连结构，在互连结构上具有第一间距的第一多个焊盘， 半导体衬底下面的第二多个衬垫，以及半导体衬底中的多个穿通衬底通孔，其中第一和第二多个焊盘通过多个贯穿衬底通孔互连。

公开(公告)号：US06719619B2

公开(公告)日：2004-04-13

申请号：US09846641

申请日：2001-05-01

申请人： Ching-Hui Kuo ,  Jheng-Tong Wu ,  Chih-Hsien Chang

发明人： Ching-Hui Kuo ,  Jheng-Tong Wu ,  Chih-Hsien Chang

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B24B45/006 ,  B24B53/12 ,  Y10T279/17411 ,  Y10T279/17752

摘要： A quick coupler for mounting a rotational disk which enables the rotational disk to be quick connect to or disconnect from a pad conditioner disk holder is disclosed. The quick coupler consists of two major components of a disk holder and a travel housing. The disk holder is formed in a ring shape having a center aperture in a polygon shape for intimately engaging a polygon-shaped shaft of the travel housing such that a rotational torque can be transmitted from the travel housing to the disk holder. Each side of the polygon is provided with a steel ball and a recessed slot behind the ball for receiving a jutting key operated by a retractable ring attached to the travel housing. The travel housing is formed in a cylindrical shape that has a first end threaded for engaging a drive means and a second end in the polygon shape.

摘要翻译： 公开了一种用于安装旋转盘的快速联接器，其使得旋转盘能够快速地连接到垫调节器盘保持器或从垫调节器盘保持器脱离。 快速耦合器由盘保持器和行进壳体的两个主要部件组成。 盘保持器形成为具有多边形形状的中心孔的环形，用于紧密地接合行进壳体的多边形轴，使得旋转扭矩可以从行驶壳体传递到盘保持器。 多边形的每一侧都设有一个钢球和一个在球后面的凹槽，用于接收一个伸出的钥匙，该钥匙由一个附着在行驶箱上的伸缩环操作。 移动壳体形成为圆柱形，其具有螺纹用于接合驱动装置的第一端和多边形形状的第二端。

公开(公告)号：US11077217B2

公开(公告)日：2021-08-03

申请号：US16215647

申请日：2018-12-11

申请人： Ming-Hsin Li ,  Su-Jung Chen ,  Ming-Wei Chen ,  Yuan-Ruei Huang ,  Shih-Ying Lee ,  Chun-Fang Feng ,  Sheng-Nan Lo ,  Chih-Hsien Chang

发明人： Ming-Hsin Li ,  Su-Jung Chen ,  Ming-Wei Chen ,  Yuan-Ruei Huang ,  Shih-Ying Lee ,  Chun-Fang Feng ,  Sheng-Nan Lo ,  Chih-Hsien Chang

IPC分类号： A61K51/08 ,  A61K51/04 ,  A61K51/06

摘要： The present invention provides a radioactive labeling method for neuropeptide Y (NPY) compound and a mammalian diagnostic radioactive targeting medicine with NPY peptide being modified at position 27th to 36th, and after binding with the chelating agent and labeling the radiation nucleus 66Ga67Ga68Ga177Lu or 111In to provide a radioactive targeting medicine for multi-type breast cancer diagnosis and treatment.

公开(公告)号：US09363115B2

公开(公告)日：2016-06-07

申请号：US13539519

申请日：2012-07-02

申请人： Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Shih-Hung Lan ,  Chih-Hsien Chang

发明人： Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Shih-Hung Lan ,  Chih-Hsien Chang

IPC分类号： G06F11/07 ,  H04L25/14 ,  G06F13/16

CPC分类号： H04L25/14 ,  G06F13/1689

摘要： Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.

摘要翻译： 公开了通过调整这些数据位的输入线的定时来对准多个数据位的系统和方法。 实施例包括用于比较多组位的定时的分层结构。 其他实施例包括在3D管芯堆叠架构中对准来自多个芯片的数据位。

公开(公告)号：US09148135B2

公开(公告)日：2015-09-29

申请号：US13532881

申请日：2012-06-26

申请人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： G06F1/00 ,  H03K5/156 ,  G06F1/08

CPC分类号： H03K5/1565 ,  G06F1/08

摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

摘要翻译： 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

公开(公告)号：US08963649B2

公开(公告)日：2015-02-24

申请号：US13731687

申请日：2012-12-31

申请人： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03L1/00 ,  H03L7/06 ,  H03B5/10

CPC分类号： H03L1/00 ,  H03B5/10 ,  H03L7/06 ,  H03L7/099 ,  H03L7/0992

摘要： A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

摘要翻译： 压控振荡器（VCO）包括电流控制振荡器，电压 - 电流转换器和感测电路。 感测电路包括延迟单元，并且感测电路被配置为响应于延迟单元的时间延迟而产生多个补偿控制信号。 电压 - 电流转换器被配置为响应于VCO控制信号和多个补偿控制信号而产生电流信号。 电流控制振荡器被配置为响应于当前信号产生振荡信号。

公开(公告)号：US20130342252A1

公开(公告)日：2013-12-26

申请号：US13532881

申请日：2012-06-26

申请人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  G06F1/08

摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

摘要翻译： 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

公开(公告)号：US20130187677A1

公开(公告)日：2013-07-25

申请号：US13355024

申请日：2012-01-20

申请人： Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

发明人： Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC分类号： G01R31/26

CPC分类号： H03K3/012 ,  G01R31/26 ,  G01R31/2607 ,  G01R31/3004 ,  G01R31/3191 ,  G01R31/31924 ,  G01R31/3193 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/0002 ,  H03K3/017 ,  H03K17/94 ,  H01L2924/00

摘要： A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

公开(公告)号：US08410818B1

公开(公告)日：2013-04-02

申请号：US13372978

申请日：2012-02-14

申请人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

发明人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC分类号： H03K19/094

CPC分类号： H03K3/012 ,  H03K19/0013 ,  H03K19/018521

摘要： A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

公开(公告)号：US07580843B2

公开(公告)日：2009-08-25

申请号：US11430702

申请日：2006-05-08

申请人： Chih-Hsien Chang ,  Chih-Wei Hung ,  Hsien-Ming Tsai

发明人： Chih-Hsien Chang ,  Chih-Wei Hung ,  Hsien-Ming Tsai

IPC分类号： G10L19/00 ,  G10L13/00 ,  G06F17/14

CPC分类号： G10L19/0208

摘要： A synthesis subband filter apparatus is provided. The apparatus is used for processing 18 sets of signals which each includes 32 subband sampling signals in accordance with a specification providing 512 window coefficients. The apparatus includes a processor for processing the 18 sets of signals in sequence. The processor further includes a converting module and a generating module. The converting module is used for converting the 32 subband sampling signals of the set of signals being processed into 32 converted vectors by use of 32-points discrete cosine transform (DCT), and writing the 32 converted vectors into 512 default vectors with a first-in, first-out queue. The generating module is used for generating 32 pulse code modulation (PCM) signals, relative to the set of signals being processed according to a set of synthesis formulae proposed in this invention.

摘要翻译： 提供合成子带滤波器装置。 该装置用于处理根据提供512个窗系数的规范的18组信号，每组信号包括32个子带采样信号。 该装置包括用于依次处理18组信号的处理器。 处理器还包括转换模块和生成模块。 转换模块用于通过使用32点离散余弦变换（DCT）将被处理的信号组的32个子带采样信号转换为32个转换的矢量，并将32个转换的矢量写入512个默认矢量， 在，先出队列。 生成模块用于产生32个脉码调制（PCM）信号，相对于根据本发明中提出的一组合成公式处理的信号集合。