公开(公告)号：US06670246B1

公开(公告)日：2003-12-30

申请号：US10465178

申请日：2003-06-19

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7926

摘要： A method for forming a vertical nitride read-only memory cell. First, a substrate having at least one trench is provided. Next, a masking layer is formed over the sidewall of the trench. Next, ion implantation is performed on the substrate to respectively form doping areas in the substrate near its surface and the bottom of the substrate trench to serve as bit lines. Next, bit line oxides are formed over each of the doping areas and an oxide layer is formed overlying the mask layer by thermal oxidation. Finally, a conductive layer is formed overlying the bit line oxides and fills in the trench to serve as a word line.

摘要翻译： 一种用于形成垂直氮化物只读存储单元的方法。 首先，提供具有至少一个沟槽的衬底。 接下来，在沟槽的侧壁上形成掩模层。 接下来，在衬底上进行离子注入，以分别在衬底的表面和底部附近在衬底中形成掺杂区域，以用作位线。 接下来，在每个掺杂区域上形成位线氧化物，并且通过热氧化在掩模层上形成氧化物层。 最后，形成覆盖位线氧化物的导电层并填充在沟槽中以用作字线。

公开(公告)号：US07576381B2

公开(公告)日：2009-08-18

申请号：US11955397

申请日：2007-12-13

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC分类号： H01L27/108

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

摘要翻译： 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US20090014773A1

公开(公告)日：2009-01-15

申请号：US11946868

申请日：2007-11-29

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

摘要翻译： 一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分 去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层， 第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽 用第二导电层打开，并移除垫。

公开(公告)号：US20080265302A1

公开(公告)日：2008-10-30

申请号：US11955397

申请日：2007-12-13

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

摘要翻译： 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US07135731B2

公开(公告)日：2006-11-14

申请号：US10707396

申请日：2003-12-10

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

摘要： A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

摘要翻译： 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。

公开(公告)号：US20060088967A1

公开(公告)日：2006-04-27

申请号：US11114735

申请日：2005-04-26

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

摘要： The present invention provides a method of manufacturing a FinFET transistor, comprising the steps of: forming a plurality of trenches in a semiconductor substrate, forming a dielectric layer on the semiconductor substrate and filling the trenches, and etching back the dielectric layer to a level below the surface of the substrate to form one or more semiconductor fins standing between the trenches as an active region, such as a source, drain, and channel for the FinFET transistor.

摘要翻译： 本发明提供一种制造FinFET晶体管的方法，包括以下步骤：在半导体衬底中形成多个沟槽，在半导体衬底上形成电介质层并填充沟槽，并将电介质层回蚀刻到低于 衬底的表面以形成一个或多个位于沟槽之间的半导体鳍片作为有源区域，例如用于FinFET晶体管的源极，漏极和沟道。

公开(公告)号：US07005701B2

公开(公告)日：2006-02-28

申请号：US10318551

申请日：2002-12-13

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L29/76 ,  H01L39/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06995061B2

公开(公告)日：2006-02-07

申请号：US10779607

申请日：2004-02-18

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

公开(公告)号：US06916715B2

公开(公告)日：2005-07-12

申请号：US10694155

申请日：2003-10-27

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/148

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US20050087823A1

公开(公告)日：2005-04-28

申请号：US10994018

申请日：2004-11-19

申请人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

摘要： A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

摘要翻译： 只读存储单元（ROM）及其制造方法。 电池包括衬底，多个位线，多个位线氧化物，栅极电介质层和字线。 在基板的表面附近形成位线。 位线氧化物位于位线之上。 栅介电层设置在位线之间的衬底上，并且还包括富硅氧化物层。 字线设置在位线氧化物和栅极电介质层之上。