公开(公告)号：US09112467B1

公开(公告)日：2015-08-18

申请号：US13652939

申请日：2012-10-16

Applicant: Cirrus Logic, Inc.

Inventor： John Christopher Tucker ,  Daniel John Allen ,  John L. Melanson ,  Ammisetti Prasad

IPC: H03F99/00 ,  H03G3/20 ,  H02M3/07 ,  H03F1/02

CPC classification number: H03G3/004 ,  H02M3/07 ,  H03F1/0227 ,  H03F1/025 ,  H03F3/183 ,  H03F2200/03 ,  H03F2200/211 ,  H03F2200/507 ,  H03G3/20 ,  H03G3/3031

Abstract: An energy-efficient consumer device audio power output stage with gain control provides improved battery life and reduced power dissipation without clipping the audio output signal. A power supply having a selectable operating mode supplies the power supply rails to the power amplified output stage. The operating mode is controlled in conformity with an input audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The gain applied to the audio input signal is reduced for a predetermined time period when a higher output voltage of the power supply is selected, to avoid clipping the audio output signal.

Abstract translation: 具有增益控制功能的节能消费电子设备音频功率输出级能够提高电池寿命，降低功耗，同时不会影响音频输出信号。 具有可选操作模式的电源将电源轨提供给功率放大输出级。 操作模式根据输入音频信号电平进行控制，输入音频信号电平可以根据设备的音量控制设置和/或从确定被放大的信号的幅度的信号电平检测器确定。 当选择电源的较高输出电压时，施加到音频输入信号的增益在预定时间段内减小，以避免削波音频输出信号。

公开(公告)号：US20150078559A1

公开(公告)日：2015-03-19

申请号：US14036136

申请日：2013-09-25

Applicant: Cirrus Logic, Inc.

Inventor： Anand Ilango ,  Daniel John Allen ,  Aniruddha Satoskar

IPC: H04R29/00

CPC classification number: H04R3/007 ,  G10K11/17854 ,  G10K11/17881 ,  G10K11/17885 ,  G10K2210/1081 ,  G10K2210/30232 ,  G10K2210/3045 ,  G10K2210/3049 ,  H03F1/0211 ,  H03F1/0227 ,  H03F1/52 ,  H03F3/181 ,  H03F3/183 ,  H03F3/185 ,  H03F3/52 ,  H03F2200/03 ,  H03F2200/462 ,  H03F2200/471 ,  H04R5/04 ,  H04R29/001 ,  H04R2420/05

Abstract: In accordance with systems and methods of the present disclosure, an audio device may include an electrical terminal, an audio circuit, and a transducer load detection circuit. The electrical terminal may couple a transducer device to the audio device. The audio circuit may generate an analog audio signal, wherein the analog audio signal is coupled to the electrical terminal The transducer load detection circuit may detect a load impedance of the transducer device when the transducer device is coupled to the audio device from characteristics measured at the electrical terminal.

公开(公告)号：US09831843B1

公开(公告)日：2017-11-28

申请号：US14204793

申请日：2014-03-11

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Bharath Kumar Thandri ,  Anand Ilango ,  Aniruddha Satoskar ,  Daniel John Allen ,  Xiaofan Fei

IPC: H04R5/00 ,  H03G3/20

CPC classification number: H03G3/20 ,  H03G3/001 ,  H03G3/002 ,  H03G3/02 ,  H03G3/3005 ,  H03G3/3026 ,  H03M1/66 ,  H03M1/70

Abstract: An audio playback path of an audio apparatus includes a digital modulator, a digital-to-analog converter (DAC), and a power amplifier. The digital modulator receives a playback signal corresponding to playback audio content and generates a digital input signal in accordance with the playback signal. The DAC receives the audio input signal and generates an analog preamplifier signal. The power amplifier generates an audio output signal in accordance with the preamplifier signal and an analog attenuation determined by the analog attenuation signal. The apparatus may include a volume control input to receive a volume control signal and a playback controller configured to perform operations including generating an analog attenuation signal in accordance with the volume control signal, monitoring a playback state indicated by the playback parameters, and responsive to detecting the playback state satisfying the playback criterion, modifying a selected playback parameter to improve a performance parameter of the playback path.

公开(公告)号：US09293986B2

公开(公告)日：2016-03-22

申请号：US14108101

申请日：2013-12-16

Applicant: Cirrus Logic, Inc.

Inventor： Bharath Kumar Thandri ,  Thuan L. Nguyen ,  Daniel John Allen ,  Lingli Zhang ,  Aniruddha Satoskar ,  Aaron Brennan ,  Dan Shen

IPC: H03F1/30 ,  H02M3/07 ,  H03F1/02

CPC classification number: H02M3/07 ,  H03F1/025 ,  H03F3/005 ,  H03F3/187 ,  H03F2200/03 ,  H03F2200/555 ,  H03F2200/78

Abstract: Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition.

Abstract translation: 可以通过在模式转换期间通过耗散来自飞行和保持电容器的电荷来减少从电荷泵到功率管理集成电路（PMIC）的启动电流。 开关可以串联放置在电荷泵和PMIC之间以断开电荷泵，并防止反冲电流到达PMIC。 此外，作为开关的附加负载可以耦合到电荷泵输出以从飞行和保持电容器消散电荷。 另外，在模式转换期间，可以使用闭合反馈回路来监测和排出来自飞行和保持电容器的过量电荷。 此外，在模式转换期间，可以在飞行和保持电容器之间重新分配电荷以减少转换的时间段。

公开(公告)号：US09276594B2

公开(公告)日：2016-03-01

申请号：US13840345

申请日：2013-03-15

Applicant: Cirrus Logic, Inc.

Inventor： Cory Jay Peterson ,  Bhoodev Kumar ,  Daniel John Allen ,  Jeffrey D. Alderson

IPC: H03L7/06 ,  H03L7/10

CPC classification number: H03L7/104

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract translation: 当预期另一信号的变化时，通过延迟时间窗外的信号传播可以降低噪声。 可以在第一时钟信号的变化和第二时钟信号的变化之间定义时间窗口，在该时间窗口期间诸如数据信号的第三信号不传播通过电路。 当第一时钟信号在第一时钟信号处于与第二时钟信号不同的电平之后，第三信号发生变化时，第三信号改变的传播可被延迟直到接收到第二时钟信号的改变。 可以通过没有亚稳态的锁存和保持电路来实现延迟传播。

公开(公告)号：US20140340158A1

公开(公告)日：2014-11-20

申请号：US14108101

申请日：2013-12-16

Applicant: Cirrus Logic, Inc.

Inventor： Bharath Kumar Thandri ,  Thuan L. Nguyen ,  Daniel John Allen ,  Lingli Zhang ,  Aniruddha Satoskar ,  Aaron Brennan ,  Dan Shen

IPC: H02M3/07 ,  H03F1/02

CPC classification number: H02M3/07 ,  H03F1/025 ,  H03F3/005 ,  H03F3/187 ,  H03F2200/03 ,  H03F2200/555 ,  H03F2200/78

Abstract: Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition.

Abstract translation: 可以通过在模式转换期间通过耗散来自飞行和保持电容器的电荷来减少从电荷泵到功率管理集成电路（PMIC）的启动电流。 开关可以串联放置在电荷泵和PMIC之间以断开电荷泵，并防止反冲电流到达PMIC。 此外，作为开关的附加负载可以耦合到电荷泵输出以从飞行和保持电容器消散电荷。 另外，在模式转换期间，可以使用闭合反馈回路来监测和排出来自飞行和保持电容器的过量电荷。 此外，在模式转换期间，可以在飞行和保持电容器之间重新分配电荷以减少转换的时间段。

公开(公告)号：US20140266337A1

公开(公告)日：2014-09-18

申请号：US13840345

申请日：2013-03-15

Applicant: Cirrus Logic, Inc.

Inventor： Cory Jay Peterson ,  Bhoodev Kumar ,  Daniel John Allen ,  Jeffrey D. Alderson

IPC: H03L7/10

CPC classification number: H03L7/104

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract translation: 当预期另一信号的变化时，通过延迟时间窗外的信号传播可以降低噪声。 可以在第一时钟信号的变化和第二时钟信号的变化之间定义时间窗口，在该时间窗口期间诸如数据信号的第三信号不传播通过电路。 当第一时钟信号在第一时钟信号处于与第二时钟信号不同的电平之后，第三信号发生变化时，第三信号改变的传播可被延迟，直到接收到第二时钟信号的改变。 可以通过没有亚稳态的锁存和保持电路来实现延迟传播。