摘要:
A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.
摘要:
A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.
摘要:
Temperatures on a chip, including particular regions of a chip are monitored by sensing changes in sub-threshold conduction of a field effect transistor (FET) integrated on the chip due to changes in charge carrier population distribution with temperature therein. Such changes in sub-threshold current with temperature are preferably detected using a current mirror and two FETs with different channel geometry and slightly different gate voltages such that the currents are equal at a specific design temperature. The slightly different gate voltages are conveniently provided by a low current voltage divider with or without on-chip voltage regulation in which resistor ratios can be accurately and repeatably obtained. Variations from that temperature thus yield large current differences and substantial signal swing which improve noise immunity. Hysteresis can be applied to the output (or amplified output) of the current mirror to obtain bistable thermostat-like action. Variant applications provide sensing at plural chip locations (e.g. for sensing temperature gradients and temperatures of autonomously operating portions of the chip) and a plurality of temperatures on the chip. Temperatures thus monitored control implementation of performance enhancing algorithms in regard to the chip.
摘要:
An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.
摘要:
A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要:
A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.
摘要:
A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要:
A semiconductor non-inverting repeater circuit utilizes a pair of current mirrors operating in a balanced source/sink operation during non-input signal periods to provide quiescent biasing current to a pair of complementary bipolar output transistors. The bipolar output transistors are configured in a complementary emitter-follower arrangement to provide minimum delay. Finally, the circuit includes two diodes and two capacitors to supply a non-inverted input signal to the bipolar output transistors such that a non-inverted output signal is produced.
摘要:
A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.