Low powering apparatus for automatic reduction of power in active and
standby modes
    11.
    发明授权
    Low powering apparatus for automatic reduction of power in active and standby modes 失效
    用于在主动和待机模式下自动降低功率的低功率设备

    公开(公告)号:US6011383A

    公开(公告)日:2000-01-04

    申请号:US120211

    申请日:1998-07-21

    IPC分类号: G06F1/32 G05F1/110 G06F1/00

    摘要: A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.

    摘要翻译: 公开了一种用于在主动和待机模式下自动降低功率的低功率设备。 低功率装置包括状态检测器,安全装置的边缘和定位装置。 状态检测器检测在最近过去占主导地位的第一或第二状态,例如待机状态和活动状态。 安全装置的边缘表示与检测到的第一或第二状态相关的安全低功率余量。 定位装置根据状态检测器的输出和安全装置的余量调整功率水平。 因此,低功率设备使系统在第一或第二状态下的功率水平最小化,而不会影响系统的全部性能。

    Low input impedance line/bus receiver
    12.
    发明授权
    Low input impedance line/bus receiver 失效
    低输入阻抗线路/总线接收器

    公开(公告)号:US06498518B1

    公开(公告)日:2002-12-24

    申请号:US09617680

    申请日:2000-07-14

    IPC分类号: H03K522

    摘要: A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.

    摘要翻译: 连接到电源端子并且具有至少一个输入端子和至少一个输出端子的电流感测电路包括至少一个具有基极,发射极和集电极的双极晶体管,连接到电源端子的至少一个电流镜放大器, 所述电流镜放大器具有连接到所述集电极并且具有连接到所述发射极的至少一个输出的输入端和连接到所述基极的DC电压源。

    On-chip thermometry for control of chip operating temperature
    13.
    发明授权
    On-chip thermometry for control of chip operating temperature 失效
    用于芯片工作温度的片上测温

    公开(公告)号:US5873053A

    公开(公告)日:1999-02-16

    申请号:US841967

    申请日:1997-04-08

    IPC分类号: G01K7/01

    CPC分类号: G01K7/01 Y10S323/907

    摘要: Temperatures on a chip, including particular regions of a chip are monitored by sensing changes in sub-threshold conduction of a field effect transistor (FET) integrated on the chip due to changes in charge carrier population distribution with temperature therein. Such changes in sub-threshold current with temperature are preferably detected using a current mirror and two FETs with different channel geometry and slightly different gate voltages such that the currents are equal at a specific design temperature. The slightly different gate voltages are conveniently provided by a low current voltage divider with or without on-chip voltage regulation in which resistor ratios can be accurately and repeatably obtained. Variations from that temperature thus yield large current differences and substantial signal swing which improve noise immunity. Hysteresis can be applied to the output (or amplified output) of the current mirror to obtain bistable thermostat-like action. Variant applications provide sensing at plural chip locations (e.g. for sensing temperature gradients and temperatures of autonomously operating portions of the chip) and a plurality of temperatures on the chip. Temperatures thus monitored control implementation of performance enhancing algorithms in regard to the chip.

    摘要翻译: 通过感测集成在芯片上的场效应晶体管(FET)的亚阈值传导的变化,由于载流子群体分布随温度的变化而监测芯片上包括芯片的特定区域的温度。 亚阈值电流随温度的这种变化优选使用电流镜和具有不同通道几何形状和略微不同的栅极电压的两个FET来检测,使得电流在特定设计温度下是相等的。 通过具有或不具有片内电压调节的低电流分压器可以方便地提供略微不同的栅极电压,其中可以精确和重复地获得电阻器比率。 因此,该温度的变化产生大的电流差异和显着的信号摆动,这提高了抗噪声性。 迟滞可应用于电流镜的输出(或放大输出),以获得双稳态恒温器状作用。 变体应用提供在多个芯片位置处的感测(例如用于感测芯片的自主操作部分的温度梯度和温度)以及芯片上的多个温度。 因此监控的温度控制了关于芯片的性能增强算法的实现。

    Integrated high-performance decoupling capacitor and heat sink
    15.
    发明授权
    Integrated high-performance decoupling capacitor and heat sink 失效
    集成高性能去耦电容和散热片

    公开(公告)号:US06548338B2

    公开(公告)日:2003-04-15

    申请号:US09764504

    申请日:2001-01-17

    IPC分类号: H01L218238

    摘要: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

    摘要翻译: 一种显着且非常有效的去耦电容器和散热器组合,其在单个结构中提供散热器和去耦电容器,其紧邻芯片上的有源电路,需要散热或去耦电容或两者兼有。 这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现,所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物 导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路,需要这种去耦电容和散热能力。 去耦电容可以使用芯片本身的衬底作为电容板之一,并且形成金属沉积物作为第二电容板,其也用作形成在芯片中的有源电路的散热器。 因此,该结构提供了重要且有效的去耦电容,其紧邻芯片上的有源电路,需要这种去耦电容,并为解耦的有源电路提供改进的散热。

    Method and apparatus for allocating data and instructions within a shared cache
    16.
    发明授权
    Method and apparatus for allocating data and instructions within a shared cache 失效
    用于在共享缓存内分配数据和指令的方法和装置

    公开(公告)号:US06532520B1

    公开(公告)日:2003-03-11

    申请号:US09394965

    申请日:1999-09-10

    IPC分类号: G06F1200

    摘要: A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.

    摘要翻译: 提供了一种方法和装置,用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。 高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数,并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。 然后,响应于检测到的预选阈值的交叉,调整统一高速缓存的替换算法,该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。 替换算法优选地是LRU算法,其中调整步骤包括递增第一类型数据线的年龄指示。 用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器,其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数,并且当计数器的计数超过时,在第一计数器输出上输出第一逻辑状态 第一预定计数。 耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态,增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

    Integrated high-performance decoupling capacitor and heat sink
    18.
    发明授权
    Integrated high-performance decoupling capacitor and heat sink 失效
    集成高性能去耦电容和散热片

    公开(公告)号:US06236103B1

    公开(公告)日:2001-05-22

    申请号:US09283828

    申请日:1999-03-31

    IPC分类号: H01L2900

    摘要: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

    摘要翻译: 一种显着且非常有效的去耦电容器和散热器组合,其在单个结构中提供散热器和去耦电容器,其紧邻芯片上的有源电路,需要散热或去耦电容或两者兼有。 这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现,所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物 导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路,需要这种去耦电容和散热能力。 去耦电容可以使用芯片本身的衬底作为电容板之一,并且形成金属沉积物作为第二电容板,其也用作形成在芯片中的有源电路的散热器。 因此,该结构提供了重要且有效的去耦电容,其紧邻芯片上的有源电路,需要这种去耦电容,并为解耦的有源电路提供改进的散热。

    Capacitor memory with an amplified cell signal
    20.
    发明授权
    Capacitor memory with an amplified cell signal 失效
    具有放大单元信号的电容器存储器

    公开(公告)号:US4168536A

    公开(公告)日:1979-09-18

    申请号:US811812

    申请日:1977-06-30

    CPC分类号: G11C11/403

    摘要: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

    摘要翻译: 产生具有串联电路的存储器,其包括电荷存储装置,阻抗和开关装置以及在电荷存储装置和阻抗之间的点处连接到串联电路的输入端和耦合到位/感测的输出的放大器 线。 开关装置由字线的脉冲控制。 串联电路将位/检测线和参考电位互连。 在优选实施例中,开关装置是其栅电极连接到字线的第一场效应晶体管,放大器是第二场效应晶体管,其栅电极连接到电荷存储装置和 该阻抗并且具有耦合到比特/感测线及其另一个载流电极的一个其载流电极耦合到参考电位点。