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11.发明授权Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices 失效包括CMOS和高压电子器件的半导体集成电路的制造方法
公开(公告)号：US4892836A
公开(公告)日：1990-01-09
申请号：US028842
申请日：1987-03-23
IPC分类号： H01L21/033 , H01L21/76 , H01L21/8234 , H01L21/8236 , H01L21/8238 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L21/8236 , H01L21/033 , H01L21/823456 , H01L27/0922
摘要： This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.
摘要翻译： 该方法需要减少数量的工艺阶段并提供有效的高电压结构，包括通过硼原子注入通过保护掩模形成CMOS器件的N沟道晶体管的P阱区域，形成 围绕所述CMOS器件的至少一个绝缘区域，形成具有与所述绝缘区域相同的导电类型但在所述绝缘区域的至少一部分上以及所述高压电子器件中的较小的杂质浓度的边缘区域，借助于所述绝缘区域 用于形成P阱区的相同的硼原子注入。
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12.发明授权Monolithically integrated semiconductor device containing bipolar junction transistors, CMOS and DMOS transistors and low leakage diodes and a method for its fabrication 失效包含双极结晶体管，CMOS和DMOS晶体管和低漏极二极管的单片集成半导体器件及其制造方法
公开(公告)号：US4887142A
公开(公告)日：1989-12-12
申请号：US276890
申请日：1988-11-28
申请人： Franco Bertotti , Carlo Cini , Claudio Contiero , Paola Galbiati
发明人： Franco Bertotti , Carlo Cini , Claudio Contiero , Paola Galbiati
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.
摘要翻译： 公开了一种单片集成半导体器件，其可以包含七个不同电路部件的样本; 即：横向N-MOS和横向P-MOS晶体管（CMOS），垂直N-DMOS和垂直P-DMOS晶体管，垂直NPN双极晶体管，具有隔离集电极和低漏极结二极管的垂直PNP双极晶体管以及用于 制造这样的装置。
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13.发明授权Manufacturing integrated circuits containing P-channel MOS transistors and bipolar transistors utilizing boron and arsenic as dopants 失效制造包含P沟道MOS晶体管的集成电路和利用硼和砷作为掺杂剂的双极晶体管
公开(公告)号：US4721686A
公开(公告)日：1988-01-26
申请号：US6037
申请日：1987-01-22
IPC分类号： H01L21/22 , H01L21/225 , H01L21/265 , H01L21/8222 , H01L21/8234 , H01L21/8236 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/78 , H01L21/38 , H01L21/425
CPC分类号： H01L21/8249 , H01L21/22 , H01L21/2253 , H01L21/2652 , H01L21/8234 , H01L21/8236 , H01L21/8238
摘要： This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by means of an appropriate mask. A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms, but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N.sup.+ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted.
摘要翻译： 相对于已知方法需要较少数量的掩模步骤的该方法包括通过适当的掩模在外延层的表面上的硼注入而不进行掩模，并且在外延层表面的预定位置进行砷注入。 然后随后的热处理导致注入的砷和硼原子的扩散，但是通过与后者的相互作用来防止在其中也发生砷注入的区域中的硼扩散，从而获得具有N +型导电性的区域，其中两个硼 已经植入了砷，并且仅植入硼的P型导电性区域。
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公开(公告)号：US07126230B2
公开(公告)日：2006-10-24
申请号：US10864901
申请日：2004-06-09
IPC分类号： H01L29/40
CPC分类号： H01L24/06 , H01L24/03 , H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05552 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.
摘要翻译： 描述了一种半导体电子器件，其包括具有多个接触焊盘的半导体材料的管芯，例如通过插入接触导线电连接到支撑件，所述多个接触焊盘包括信号焊盘和电源焊盘，该器件的特征在于所述 信号焊盘实现在半导体材料的裸片上，其相互间距低于所述电源焊盘之间的间距。
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公开(公告)号：US20050035468A1
公开(公告)日：2005-02-17
申请号：US10864901
申请日：2004-06-09
IPC分类号： H01L23/485 , H01L23/48
CPC分类号： H01L24/06 , H01L24/03 , H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05552 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.
摘要翻译： 描述了一种半导体电子器件，其包括具有多个接触焊盘的半导体材料的管芯，例如通过插入接触导线电连接到支撑件，所述多个接触焊盘包括信号焊盘和电源焊盘，该器件的特征在于所述 信号焊盘实现在半导体材料的裸片上，其相互间距低于所述电源焊盘之间的间距。
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16.发明授权Process for the fabrication of semiconductor devices having various buried regions 失效具有各种埋置区域的半导体器件的制造方法
公开(公告)号：US5789288A
公开(公告)日：1998-08-04
申请号：US854584
申请日：1997-05-12
IPC分类号： H01L21/265 , H01L21/266 , H01L21/74 , H01L21/8249
CPC分类号： H01L21/266 , H01L21/74 , H01L21/8249
摘要： A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it. The process described allows the production of integrated devices with an additional buried layer while utilizing one fewer mask than conventional processes.
摘要翻译： 一种用于通过形成氮化硅层（52）来掺杂P型衬底（50）的方法，通过该层注入N型杂质（图7），形成抗蚀剂掩模（54），其离开至少一个区域 （图8），包含暴露的氮化物层的一部分，首先用不足的能量注入N型杂质，然后以足够的能量穿过氮化物层，使衬底（图9）高 在氧化环境中进行温度处理以在未被氮化物层覆盖的衬底的区域上形成二氧化硅焊盘（55），去除氮化物层并且将P型杂质注入到由衬垫限定的区域中。 然后，该过程继续移除焊盘，并且以常规方式，形成外延层并选择性地掺杂以在其中形成P型和N型区域。 所描述的方法允许使用附加掩埋层的集成器件的生产，同时使用比常规工艺少的掩模。
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17.发明授权
公开(公告)号：US5629558A
公开(公告)日：1997-05-13
申请号：US454647
申请日：1995-05-31
IPC分类号： H01L21/329 , H01L29/861 , H01L27/06 , H01L29/00 , H01L31/0352
CPC分类号： H01L29/66128 , H01L29/8611
摘要： A diode integrated on semiconductor material with BCD technology and of the type provided on a substrate having a first type of conductivity inside an isolation region having a second type of conductivity. The diode comprises also a buried anode region having a first type of conductivity and a cathode region having a second type of conductivity. The cathode region comprises an epitaxial layer located above the buried anode region and a highly doped region provided inside the epitaxial layer. The buried anode region comprises depressions opposite which is located the highly doped region with the depressions being achieved by the intersection of lateral diffusions of distinct and adjacent portions of the buried anode region.
摘要翻译： 集成在具有BCD技术的半导体材料上的二极管，并且具有在具有第二类导电性的隔离区域内具有第一类型导电性的基板上提供的类型的二极管。 二极管还包括具有第一类导电性的掩埋阳极区域和具有第二类导电性的阴极区域。 阴极区域包括位于掩埋阳极区域上方的外延层和设置在外延层内部的高掺杂区域。 掩埋阳极区域包括相对的凹陷，其位于高掺杂区域，凹陷通过掩埋阳极区域的不同相邻部分的横向扩散的交叉来实现。
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18.发明授权公开(公告)号：US06271567B1
公开(公告)日：2001-08-07
申请号：US09227946
申请日：1999-01-11
申请人： Massimo Pozzoni , Paolo Cordini , Domenico Rossi , Giorgio Pedrazzini , Paola Galbiati , Michele Palmieri , Luca Bertolini
发明人： Massimo Pozzoni , Paolo Cordini , Domenico Rossi , Giorgio Pedrazzini , Paola Galbiati , Michele Palmieri , Luca Bertolini
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.
摘要翻译： 在包括功率DMOS晶体管的结隔离集成电路中，形成在相应的阱区域中或者在相反导电类型的衬底上的隔离的外延区域中形成的电路形成在对供过剩和/或地下效应敏感的不同隔离区域中。 这些影响是由耦合到电源轨或地的各个功率DMOS晶体管引起的。 这些效果可以通过特定形状的布置布置来替代地控制，并且可以被有效地保护免受两种影响。 这通过介于敏感电路的区域和包含不形成替代可实施的电路布置的功率DMOS晶体管的区域来实现，该区域包含耦合到电源轨的功率DMOS晶体管或接地导轨， 可替代地实施的布置形成。 特殊插件将灵敏电路与供电或地下效应不受特定电路布置的电源设备分离和屏蔽。
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公开(公告)号：US06538281B2
公开(公告)日：2003-03-25
申请号：US09862750
申请日：2001-05-22
IPC分类号： H01L31119
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/41758 , H01L29/41775 , H01L29/4238 , H01L29/456
摘要： An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.
摘要翻译： LDMOS结构形成在半导体衬底的第一导电类型的区域中，并且包括栅极，漏极区域和源极区域。 源极区域由第一区域内的第二导电类型的体扩散形成，并且第一类型的导电性的源极扩散在体扩散内。 第二类导电性的电连接扩散是源极区域的有限区域，并且延伸穿过源极扩散并且向下延伸到身体扩散。 源扩散和电连接扩散至少有一个源触点。 LDMOS结构还包括在源极区域的整个区域上的硅化物层，使源扩散和电连接扩散短路。 源极接触形成在硅化物层上。
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公开(公告)号：US5940700A
公开(公告)日：1999-08-17
申请号：US725590
申请日：1996-10-03
IPC分类号： H01L21/329 , H01L29/861 , H01L21/8234
CPC分类号： H01L29/66128 , H01L29/8611
摘要： A diode integrated on semiconductor material with BCD technology and of the type provided on a substrate having a first type of conductivity inside an isolation region having a second type of conductivity. The diode comprises also a buried anode region having a first type of conductivity and a cathode region having a second type of conductivity. The cathode region comprises an epitaxial layer located above the buried anode region and a highly doped region provided inside the epitaxial layer. The buried anode region comprises depressions opposite which is located the highly doped region with the depressions being achieved by the intersection of lateral diffusions of distinct and adjacent portions of the buried anode region.
摘要翻译： 集成在具有BCD技术的半导体材料上的二极管，并且具有在具有第二类导电性的隔离区域内具有第一类型导电性的基板上提供的类型的二极管。 二极管还包括具有第一类导电性的掩埋阳极区域和具有第二类导电性的阴极区域。 阴极区域包括位于掩埋阳极区域上方的外延层和设置在外延层内部的高掺杂区域。 掩埋阳极区域包括相对的凹陷，其位于高掺杂区域，凹陷通过掩埋阳极区域的不同相邻部分的横向扩散的交叉来实现。
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