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公开(公告)号:US20210407881A1
公开(公告)日:2021-12-30
申请号:US17469091
申请日:2021-09-08
Applicant: DENSO CORPORATION
Inventor: Shoichiro OMAE , Hiroshi ISHINO
IPC: H01L23/367 , H01L23/495 , H01L23/31 , H01L23/00
Abstract: A semiconductor device includes: a semiconductor element having a first main electrode and a second main electrode; a first heat dissipation member and a second heat dissipation member; and a lead frame including a first main terminal connected to the first heat dissipation member and a second main terminal connected to the second main electrode. The second main terminal includes a connection portion connected with the second main electrode, a facing portion extending from the connection portion and facing the first heat dissipation member, and a non-facing portion. The non-facing portion and the first main terminal are arranged in a direction orthogonal to a thickness direction. A side surface of the first main terminal and a side surface of the non-facing portion of the second main terminal face each other.
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公开(公告)号:US20210407875A1
公开(公告)日:2021-12-30
申请号:US17468952
申请日:2021-09-08
Applicant: DENSO CORPORATION
Inventor: Ryota MIWA , Takuo NAGASE , Hiroshi ISHINO
IPC: H01L23/31 , H01L23/00 , H01L25/065 , H01L23/495
Abstract: A semiconductor device includes at least one semiconductor element, a sealing resin body, a first main terminal, and a second main terminal. The at least one semiconductor element has, as main electrodes, a first main electrode and a second main electrode. A main current flows between the first main electrode and the second main electrode. The sealing resin body seals the at least one semiconductor element. The first main terminal is electrically connected to the first main electrode inside the sealing resin body. The second main terminal is electrically connected to the second main electrode inside the sealing resin body. Each of the first main terminal and the second main terminal extends to an outside of the sealing resin body for connecting to an external member.
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公开(公告)号:US20210143088A1
公开(公告)日:2021-05-13
申请号:US17155696
申请日:2021-01-22
Applicant: DENSO CORPORATION
Inventor: Kosuke KAMIYA , Ryota TANABE , Tomohisa SANO , Takuo NAGASE , Hiroshi ISHINO , Shoichiro OMAE
IPC: H01L23/495 , H01L23/31 , H01L23/00 , H01L25/07 , H01L25/18
Abstract: A semiconductor device configures one arm of an upper-lower arm circuit, and includes: a semiconductor element that includes a first main electrode and a second main electrode, wherein a main current between the first main electrode and the second main electrode; and multiple main terminals that include a first main terminal connected to the first main electrode and a second main terminal connected to the second main electrode. The first main terminal and the second main terminal are placed adjacent to each other; A lateral surface of the first main terminal and a lateral surface of the second main terminal face each other in one direction orthogonal to a thickness direction of the semiconductor element.
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公开(公告)号:US20190088568A1
公开(公告)日:2019-03-21
申请号:US16088093
申请日:2017-04-27
Applicant: DENSO CORPORATION
Inventor: Hiroshi ISHINO , Hideki KAWAHARA , Shinji HIRAMITSU , Shunsuke ARAI
Abstract: In a semiconductor device, a plurality of semiconductor chips included in an upper-arm circuit are connected in parallel between a pair of upper-arm plates, while a plurality of semiconductor chips included in a lower-arm circuit are connected in parallel between a pair of lower-arm plates. In each of the arm circuits, the plurality of semiconductor chips are arranged in a direction perpendicular to a direction in which emitter electrodes and pads are arranged, the pads are disposed on the same side of the emitter electrodes, and signal terminals extend in the same direction. A series-connecting part between the upper- and lower-arm circuits includes a joint part 20 continued to respective side surfaces of the corresponding upper- and lower-arm plates. Each of inductances of respective parallel-connecting parts of the upper- and lower-arm plates which connect the semiconductor chips in parallel is smaller than an inductance of the series-connecting part.
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公开(公告)号:US20170148770A1
公开(公告)日:2017-05-25
申请号:US15129860
申请日:2015-03-26
Applicant: DENSO CORPORATION
Inventor: Hiroshi ISHINO , Tomokazu WATANABE
IPC: H01L25/07 , H01L25/18 , H01L23/492 , H02M7/5387 , H01L23/31 , H01L23/04 , H01L23/00 , H01L23/367 , H01L23/498
CPC classification number: H01L25/072 , H01L23/04 , H01L23/3121 , H01L23/3675 , H01L23/492 , H01L23/49838 , H01L24/48 , H01L25/07 , H01L25/18 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48106 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H02M7/003 , H02M7/48 , H02M7/5387 , H02P27/06 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/85399
Abstract: A semiconductor module includes upper arms and lower arms for three phases, heat sinks, a main circuit side bus bar, an output terminal side bus bar, a control terminal, and a resin mold portion. The output terminal side bus bar includes U-phase to W-phase wiring layers disposed opposite to each other via an insulating layer and U to W terminals electrically connecting each of the U-phase to W-phase wiring layer and a load. A stacked layer number of the U-phase to W-phase wiring layer is set to be an even number.
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公开(公告)号:US20160211741A1
公开(公告)日:2016-07-21
申请号:US14915290
申请日:2014-09-01
Applicant: DENSO CORPORATION
Inventor: Hiroshi ISHINO , Yousuke JINSEI , Atsushi IKEGAME
CPC classification number: H02M1/34 , H01L2224/05554 , H01L2224/371 , H01L2224/37147 , H01L2224/40137 , H01L2224/48247 , H01L2924/181 , H02M7/003 , H02M7/537 , H02M2001/348 , H05K7/209 , H01L2924/00012
Abstract: A power conversion device is capable of achieving three requirements to restrict a surge voltage, ensure high radiation performance of SW elements, and restrict ringing at the same time. In a power conversion device, element modules of two SW elements are stacked in a thickness direction via an insulating layer in such a manner that lateral surfaces are aligned parallel to each other in a same orientation, and a positive terminal of one SW element and a negative terminal of the other SW element are disposed so as to overlap each other in the thickness direction.
Abstract translation: 电力转换装置能够达到限制浪涌电压的三个要求,确保SW元件的高辐射性能,同时限制振铃。 在功率转换装置中,两个SW元件的元件模块通过绝缘层沿厚度方向堆叠,使得侧表面以相同的取向彼此平行排列,并且一个SW元件和 另一个SW元件的负极端子在厚度方向上彼此重叠地配置。
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