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公开(公告)号：US07889539B2
公开(公告)日：2011-02-15
申请号：US12653486
申请日：2009-12-14
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
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公开(公告)号：US07082052B2
公开(公告)日：2006-07-25
申请号：US10773549
申请日：2004-02-06
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/14
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。
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公开(公告)号：US07394679B2
公开(公告)日：2008-07-01
申请号：US11473005
申请日：2006-06-22
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。
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公开(公告)号：US20050231992A1
公开(公告)日：2005-10-20
申请号：US11151880
申请日：2005-06-13
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31
摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.
摘要翻译： 具有多个内存层的可重写内存。 只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。 通过多层共享逻辑可以重新使用驱动程序集。
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公开(公告)号：US20060018149A1
公开(公告)日：2006-01-26
申请号：US10895218
申请日：2004-07-20
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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公开(公告)号：US20060245241A1
公开(公告)日：2006-11-02
申请号：US11478520
申请日：2006-06-29
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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公开(公告)号：US20080002483A1
公开(公告)日：2008-01-03
申请号：US11725045
申请日：2007-03-16
IPC分类号： G11C7/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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公开(公告)号：US20080002473A1
公开(公告)日：2008-01-03
申请号：US11707340
申请日：2007-02-16
IPC分类号： G11C16/28
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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公开(公告)号：US20060166430A1
公开(公告)日：2006-07-27
申请号：US11369663
申请日：2006-03-06
IPC分类号： H01L21/8238
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.
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公开(公告)号：US20050111263A1
公开(公告)日：2005-05-26
申请号：US11012059
申请日：2004-12-13
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/77
摘要： Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage can be approximately equal to the average of the first select voltage and the second select voltage.
摘要翻译： 交叉点存储器阵列使用不同的电压。 本发明是一种交叉点存储器阵列，其在一个导电阵列线上施加第一选择电压，在第二导电阵列线上施加第二选择电压，两个导电阵列线是唯一限定的。 此外，未选择的电压被施加到未选择的导电阵列线。 可以在选择过程之前，之后或期间施加取消选择电压。 非选择电压可以近似等于第一选择电压和第二选择电压的平均值。
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