公开(公告)号：US07769854B2

公开(公告)日：2010-08-03

申请号：US11943016

申请日：2007-11-20

申请人： Anlu Yan ,  Tong Liu

发明人： Anlu Yan ,  Tong Liu

IPC分类号： G06F15/173

CPC分类号： H04L47/781 ,  H04L47/70 ,  H04L47/829

摘要： A technique determines whether configured logical bandwidth allotments for logical channels are supported by maximum available physical bandwidths of physical channels assigned to those logical channels. The technique establishes a bandwidth-constraint directed acyclic graph (DAG) or “BCD” based on novel relationship rules between vertexes of the BCD that represent logical channels or unions of logical channels as well as the underlying physical channels and their maximum available bandwidth constraints. Once the BCD is established, the vertexes of the BCD may be traversed (e.g., from in-neighbor vertexes to out-neighbor vertexes) to determine whether their constraints are met.

摘要翻译： 技术确定逻辑信道的配置逻辑带宽分配是否被分配给这些逻辑信道的物理信道的最大可用物理带宽支持。 该技术基于表示逻辑信道的逻辑信道或联合以及底层物理信道及其最大可用带宽约束的BCD顶点之间的新关系规则，建立了带宽约束有向非循环图（DAG）或“BCD”。 一旦BCD建立，BCD的顶点可以被遍历（例如，从邻近顶点到邻近顶点），以确定它们的约束是否被满足。

公开(公告)号：US20090290040A1

公开(公告)日：2009-11-26

申请号：US12453501

申请日：2009-05-13

申请人： Cheng Du ,  Tong Liu ,  Gang Wang ,  Zhongchao Shi ,  Tao Li

发明人： Cheng Du ,  Tong Liu ,  Gang Wang ,  Zhongchao Shi ,  Tao Li

IPC分类号： H04N5/228 ,  G06K9/36

CPC分类号： H04N5/243 ,  G06T5/009 ,  H04N5/20

摘要： A method of compressing an original dynamic range of an original image, includes a first step of obtaining a reduced image corresponding to the original image by performing quantization and downsampling on the original image that has been input; a second step of calculating a look-up table based on the reduced image, wherein the look-up table indicates a mapping relationship between the original dynamic range of the original image and a dynamic range of a medium; and a third step of mapping each of the pixels in the original image from the original dynamic range of the original image onto the dynamic range of the medium based on the look-up table.

摘要翻译： 一种压缩原始图像的原始动态范围的方法包括：通过对已经输入的原始图像进行量化和下采样来获得与原始图像相对应的缩小图像的第一步骤; 基于缩小图像计算查找表的第二步骤，其中查找表指示原始图像的原始动态范围与介质的动态范围之间的映射关系; 以及第三步骤，基于查找表将原始图像中的每个像素从原始图像的原始动态范围映射到介质的动态范围。

公开(公告)号：US20090252803A1

公开(公告)日：2009-10-08

申请号：US12338966

申请日：2008-12-18

申请人： Zhi YUAN ,  Wei Huang ,  Qin Tian ,  Chuangnian Zhang ,  Liang Han ,  Tong Liu ,  Yue Zhang ,  Yue Chen

发明人： Zhi YUAN ,  Wei Huang ,  Qin Tian ,  Chuangnian Zhang ,  Liang Han ,  Tong Liu ,  Yue Zhang ,  Yue Chen

IPC分类号： A61K9/14 ,  A61P35/00

CPC分类号： A61K9/5146 ,  A61K9/5161 ,  A61K9/5192 ,  A61K47/593 ,  A61K47/60 ,  A61K47/61 ,  A61K47/645 ,  A61K47/6935 ,  Y10S977/773 ,  Y10S977/906

摘要： Disclosed are a hepatic targeted drug delivery system and a process for preparing the same. Also disclosed is a method for treating liver cancer.

摘要翻译： 公开了肝靶向药物递送系统及其制备方法。 还公开了一种治疗肝癌的方法。

公开(公告)号：US20080253510A1

公开(公告)日：2008-10-16

申请号：US12089885

申请日：2005-10-13

申请人： Tong Liu

发明人： Tong Liu

IPC分类号： G01N23/04

CPC分类号： G01N23/046 ,  A61B6/583 ,  G01N2223/419

摘要： A computed tomography system having a fixed X-ray source [10] for producing a fan beam [20], a fixed digital detector [12] and a manipulator [14] for holding and rotating an object [16] to be inspected. Left and right projections of the rotated object on the fixed digital detector are used to determine a central ray, reconstruction of an image of the object being based on the central ray position. A corresponding method and apparatus are also disclosed.

摘要翻译： 一种计算机断层摄影系统，具有用于产生风扇光束的固定X射线源[10]，固定数字检测器[12]和用于保持和旋转要检查的物体[16]的操纵器[14]。 旋转对象在固定数字检测器上的左右投影用于确定中心射线，基于中心射线位置重建物体的图像。 还公开了相应的方法和装置。

公开(公告)号：US06870396B2

公开(公告)日：2005-03-22

申请号：US10429004

申请日：2003-04-30

申请人： Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

发明人： Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

摘要翻译： 一种装置包括现场可编程门阵列（FPGA）。 FPGA包括第一FPGA片，并且第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。 多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。 常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。 通过根据指示符存放交换机来最大化常规路由结构的可路由性。 这种新颖的指定方法与大约一半的开关提供相同的可路由性。 因此，实现了路由区域的进一步减少。 多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。

公开(公告)号：US06800884B1

公开(公告)日：2004-10-05

申请号：US10334393

申请日：2002-12-30

申请人： Sheng Feng ,  Tong Liu ,  Jung-Cheun Lien

发明人： Sheng Feng ,  Tong Liu ,  Jung-Cheun Lien

IPC分类号： H01L2710

CPC分类号： H03K19/17736 ,  H01L27/118

摘要： The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate array tiles are arranged in an array of rows and columns. Each of said field programmable gate array tiles comprises a plurality of functional groups and a plurality of interface groups, and a primary routing structure. The primary routing structure is coupled to said functional groups and interface groups and is configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive primary input signals, perform a logic operation, and generate primary output signals. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus and a vertical bus. A horizontal buffer is located between each column of field programmable gate array tiles and is coupled to the primary routing structure. A vertical buffer is located between each row of field programmable gate array tiles and is coupled to the primary routing structure.

摘要翻译： 本发明涉及一种用于现场可编程门阵列的块间缓冲系统。 现场可编程门阵列由以下组成。 多个现场可编程门阵列瓦片被布置成行和列的阵列。 每个所述现场可编程门阵列瓦片包括多个功能组和多个接口组以及主要路由结构。 主路由结构耦合到所述功能组和接口组，并被配置为接收主要输出信号，在所述至少一个现场可编程门阵列瓦片内路由主输出信号，并向所述功能组和接口组提供初级输入信号。 每个功能组被配置为接收主要输入信号，执行逻辑运算并产生主要输出信号。 每个接口组被配置为将信号从所述主路由结构传送到所述至少一个现场可编程门阵列瓦片外部，并且包括多个输入多路复用器，其被配置为选择从所述至少一个现场可编程门阵列瓦片外部接收的信号 并向所述至少一个现场可编程门阵列瓦片内的主路由结构提供信号。 所述主路由结构包括水平总线和垂直总线。 水平缓冲器位于每列现场可编程门阵列瓦片之间，并耦合到主路由结构。 垂直缓冲器位于每行现场可编程门阵列瓦片之间，并耦合到主路由结构。

公开(公告)号：US06744278B1

公开(公告)日：2004-06-01

申请号：US10061951

申请日：2002-01-31

申请人： Tong Liu ,  Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Naihui Liao

发明人： Tong Liu ,  Jung-Cheun Lien ,  Sheng Feng ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Naihui Liao

IPC分类号： H03K19177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

公开(公告)号：US06731133B1

公开(公告)日：2004-05-04

申请号：US10077190

申请日：2002-02-15

申请人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

发明人： Sheng Feng ,  Jung-Cheun Lien ,  Eddy C. Huang ,  Chung-Yuan Sun ,  Tong Liu ,  Naihui Liao

IPC分类号： H03K19177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

摘要： A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile. The first FPGA tile also comprising a secondary routing structure independent of the regular routing structure, coupled to each of the IGs, configured to transfer signals from said first FPGA tile to at least one other FPGA tile. The disclosed apparatus also provides for a routing structure between IGs and RAM blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understand that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 一种现场可编程门阵列（FPGA），包括：第一FPGA片，所述第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。 多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。 常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。 多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。 每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。 第一FPGA片还包括独立于常规路由结构的辅路由结构，耦合到每个IG，被配置为将信号从所述第一FPGA片传送到至少另一个FPGA片。 所公开的装置还提供了IG和RAM块之间的路由结构。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交的理由是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US09792985B2

公开(公告)日：2017-10-17

申请号：US14233911

申请日：2012-07-23

申请人： Marius Orlowski ,  Tong Liu ,  Mohini Verma ,  Yuhong Kang

发明人： Marius Orlowski ,  Tong Liu ,  Mohini Verma ,  Yuhong Kang

IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C14/00 ,  G11C11/54

CPC分类号： G11C13/0069 ,  G11C11/54 ,  G11C13/0004 ,  G11C13/0011 ,  G11C14/00 ,  G11C2013/0071 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146

摘要： A resistive floating electrode device (RFED) provides a logic cell or non-volatile storage or dynamic or static random access memory on an extremely compact matrix with individual cells scalable to the minimum available lithographic feature size regime by providing atomic switches connected in anti-parallel relationship, preferably with a common inert electrode. Programming is facilitated by limiting current to a compliance current level in order to maintain an OB state from which the cell can be written to either the 0 or 1 state. A perfecting feature of the invention provides for selective operation of a cell as a diode or in a volatile or non-volatile storage mode within the same memory array. A series connection of three or more RFEDs in accordance with the invention having different ON state currents, OFF state currents and reset currents can be used as adaptive, neural or chaotic logic cells.

公开(公告)号：US09311542B2

公开(公告)日：2016-04-12

申请号：US14025008

申请日：2013-09-12

申请人： Dianchao Liu ,  Yuan Liu ,  Tong Liu ,  Zhongchao Shi ,  Gang Wang

发明人： Dianchao Liu ,  Yuan Liu ,  Tong Liu ,  Zhongchao Shi ,  Gang Wang

IPC分类号： G06K9/00

CPC分类号： G06K9/00798 ,  G06K9/00208 ,  G06K9/00791 ,  G06K9/00805

摘要： A method and an apparatus for detecting a continuous road partition with a height that includes obtaining disparity maps having the continuous road partition, and U-disparity maps corresponding to the disparity maps; obtaining an intermediate detection result of the continuous road partition detected from the U-disparity maps of first N frames; and detecting the continuous road partition from the U-disparity map of a current frame, based on the obtained intermediate detection result.

摘要翻译： 一种用于检测具有高度的连续道路分隔的方法和装置，所述高度包括获得具有连续道路分隔的视差图和对应于视差图的U视差图; 从前N帧的U视差图中获取连续道路分区的中间检测结果; 并根据获得的中间检测结果，根据当前帧的U视差图检测连续道路分割。