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98 条记录 (耗时 0.023 秒)

    Circuit configuration for generating a reference voltage for reading a ferroelectric memory
    11.
    发明授权
    Circuit configuration for generating a reference voltage for reading a ferroelectric memory 有权
    用于产生用于读取铁电存储器的参考电压的电路配置

    公开(公告)号：US06392918B2

    公开(公告)日：2002-05-21

    申请号：US09817578

    申请日：2001-03-26

    申请人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

    发明人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

    摘要翻译： 用于产生用于读出的参考电压的电路和用于经由位线从铁电存储器的存储单元以恒定板电压读出的读取输出信号的评估。 在该电路中，参考电压装置由经受互补信号的作用的两个参考单元形成。 可以同时读出参考单元，以便在选择和评估装置中产生参考电压。

    Gate circuit having MOS transistors
    14.
    发明授权
    Gate circuit having MOS transistors 失效
    具有MOS晶体管的栅极电路

    公开(公告)号：US5030861A

    公开(公告)日：1991-07-09

    申请号：US445687

    申请日：1989-11-16

    申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus

    发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus

    IPC分类号： H03K17/693 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38 ,  H03K19/096 ,  H03K19/173

    CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C29/36 ,  H03K19/1736

    摘要： A circuit gives each of the input signals at its inputs to a common circuit previously charged to a supply voltage through transfer transistors. When the logical condition is satisfied the common circuit remains charged; otherwise the charge changes. This is detected by a discriminator circuit and the result is indicated at the circuit output. The circuit may be of AND-, OR-, NAND- and NOR design.

    摘要翻译： PCT No.PCT / DE88 / 00158 Sec。 371日期：一九八九年十一月十六日 102（e）日期1989年11月16日PCT提交1988年3月15日PCT Pub。 出版物WO88 / 07292 日期1988年9月22日。电路将其输入端的每个输入信号提供给预先通过传输晶体管充电到电源电压的公共电路。 当满足逻辑条件时，公共电路保持充电; 否则收费变动。 这由鉴频器电路检测，结果在电路输出端指示。 该电路可以是AND-，OR-，NAND-和NOR设计。

    Arrangement, in particular an analog-digital converter and method of operation thereof
    16.
    发明授权
    Arrangement, in particular an analog-digital converter and method of operation thereof 失效
    布置，特别是模拟数字转换器及其操作方法

    公开(公告)号：US4180806A

    公开(公告)日：1979-12-25

    申请号：US834786

    申请日：1977-09-19

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： H03M1/00 ,  H03K13/02

    CPC分类号： H03M1/361

    摘要： An arrangement, particularly an analog-digital converter having a resistance line or chain, and a plurality of voltage comparators, each preferably comprising an insulator-layer, field-transistor and a load element in the form of a resistance, capacitor or diode, in which the control electrode terminal of each transistor forms a first comparator input, which is connected to a respective point on the resistance and with each cooperable load element being connected to one of the two remaining transistor terminals, one of which also simultaneously forms the output of such voltage comparator, and with the second comparator input for such voltage comparator being formed by the other transistor terminal. Preferably, the transistors are formed on a semiconductor substrate which has doped areas forming respective source and drain electrodes with the associated gate electrodes being disposed in insulated relation to the semiconductor substrate and formed of an electrical resistance material which serially interconnects the adjacent gate electrodes of the transistors, with one of the doped electrodes of each transistor comprising a respective part of a continuously doped area of the semiconductor substrate which thus forms a common terminal for all transistors, while the other doped electrode of each transistor extends outwardly away from such common terminal to form respective individual terminals. The invention also includes the method of operating such structures.

    摘要翻译： 一种布置，特别是具有电阻线或链的模拟数字转换器和多个电压比较器，每个电压比较器优选地包括电阻，电容器或二极管形式的绝缘体层，场效应晶体管和负载元件， 每个晶体管的控制电极端子形成第一比较器输入，其连接到电阻上的相应点，并且每个可配合的负载元件连接到两个剩余晶体管端子中的一个，其中之一还同时形成 这种电压比较器，以及用于这种电压比较器的第二比较器输入由另一个晶体管端子形成。 优选地，晶体管形成在具有形成相应的源极和漏极的掺杂区域的半导体衬底上，其中相关联的栅极电极以与半导体衬底绝缘的关系设置，并且由电阻材料形成，该电阻材料将 晶体管，其中每个晶体管的掺杂电极之一包括半导体衬底的连续掺杂区域的相应部分，由此形成用于所有晶体管的公共端子，而每个晶体管的另一个掺杂电极从该公共端子向外延伸到 形成各自的终端。 本发明还包括操作这种结构的方法。

    Regenerating amplifier for CCD arrangements
    17.
    发明授权
    Regenerating amplifier for CCD arrangements 失效
    再生CCD放大器放大器

    公开(公告)号：US4082963A

    公开(公告)日：1978-04-04

    申请号：US717703

    申请日：1976-08-25

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： G11C27/04 ,  G11C11/24 ,  G11C11/34 ,  G11C19/28 ,  H01L29/768 ,  H03K5/02 ,  H01L29/78

    CPC分类号： G11C19/28 ,  G11C11/24 ,  G11C11/34 ,  G11C19/285 ,  H01L29/76825 ,  H03K5/023

    摘要： Regenerating amplifier for use with charge coupled devices comprising a pair of diode-coupled transistors connected to an output terminal of one charge coupled device, two capacitances, and means for precharging said two capacitances. One of the capacitances is a parasitic capacitance, the other of which is the input capacitance of the second charge coupled device. The charge is transferred from the output terminal of the first charge coupled device by discharging one precharged capacitor and thus discharging or not discharging the second capacitance at the input to the second charge coupled device, depending upon the binary state of the data being transferred.

    Method for improving the read signal in a memory having passive memory elements
    19.
    发明申请
    Method for improving the read signal in a memory having passive memory elements 有权
    一种用于在具有无源存储器元件的存储器中改善读取信号的方法

    公开(公告)号：US20050128796A1

    公开(公告)日：2005-06-16

    申请号：US11004880

    申请日：2004-12-07

    申请人： Kurt Hoffmann

    发明人： Kurt Hoffmann

    IPC分类号： G11C7/10 ,  G11C11/14 ,  G11C11/00

    CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C11/14 ,  G11C2211/5647

    摘要： A method for improving read signals in a memory including passive memory elements provided at crossover locations of word and bit lines, and in which stored digital information is represented by a respective resistance of the memory elements includes: determining logic levels of information bits to be written to the memory elements associated with a respective bit line; inverting the logic levels of the information bits if more than half of information bits to be written to the memory elements associated with the respective bit line have a logic level corresponding to a low-value resistance of the memory elements; writing the information bits to the memory elements; and generating an additional check bit, a logic level of which represents an inverted or non-inverted state of the information bits.

    摘要翻译： 一种用于改善存储器中的读取信号的方法，包括在字和位线的交叉位置处提供的无源存储器元件，并且其中存储的数字信息由存储器元件的相应电阻表示，包括：确定要写入的信息位的逻辑电平 到与相应位线相关联的存储器元件; 如果要写入到与相应位线相关联的存储器元件的信息位的一半以上具有与存储器元件的低值电阻相对应的逻辑电平，则反转信息位的逻辑电平; 将信息位写入存储元件; 并产生附加校验位，其逻辑电平表示信息位的反相或非反相状态。