公开(公告)号：US5159206A

公开(公告)日：1992-10-27

申请号：US561536

申请日：1990-07-31

Applicant: Ching-Yuh Tsay ,  Donald J. Redwine

Inventor： Ching-Yuh Tsay ,  Donald J. Redwine

IPC: G11C5/14 ,  G11C11/4076 ,  H03K17/22

CPC classification number: H03K17/223 ,  G11C11/4076 ,  G11C5/147

Abstract: A circuit to generate a power up reset pulse for a semiconductor device, such as a dynamic random access memory (DRAM) that may utilize an on chip voltage generator is disclosed. The circuit generates a positive going pulse when the external power supply ramps up. The pulse disappears when the voltage level within the device reaches a predetermined value of the external supply voltage. The circuit includes a CMOS inverter that is biased between the external voltage and ground and has its input coupled to the internally regulated voltage. The gate of a pull down transistor may couple the input of the CMOS inverter to the internally regulated voltage. A pull up transistor that is biased by the external voltage and whose gate is connected to the output of the CMOS inverter, is connected to the input of the CMOS inverter. Other elements may be added to enhance the circuits performance. The trip point of the circuit with respect to the externally supplied voltage may be adjusted by varying the relative sizes of the pull down transistor and the pull up transistor.

公开(公告)号：US5109258A

公开(公告)日：1992-04-28

申请号：US220425

申请日：1988-07-13

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L21/321 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1085 ,  H01L21/32105 ,  H01L27/10805

Abstract: A dynamic read/write memory cell for the one transistor N-channel silicon gate type is made by an improved process employing selective oxidation of polysilicon using. PN junction capacitors. A relatively flat surface results from the process, which is favorable to patterning small geometries. The PN junction storage capacitors have improved alpha particle protection. Metal-to-polysilicon gate contacts are made at silicide areas over polysilicon gates; the silicide lowers resistance of the poly elements.

Abstract translation: 用于一晶体管N沟道硅栅型的动态读/写存储单元是通过使用多晶硅的选择性氧化的改进方法制成的。 PN结电容。 相对平坦的表面由该方法产生，这有利于图案化的几何形状。 PN结储存电容器具有改进的α粒子保护。 金属到多晶硅栅极触点在多晶硅栅极的硅化物区域上制成; 硅化物降低了多元素的电阻。

公开(公告)号：US4688197A

公开(公告)日：1987-08-18

申请号：US566860

申请日：1983-12-30

Applicant: Mark F. Novak ,  Karl M. Guttag ,  Donald J. Redwine

Inventor： Mark F. Novak ,  Karl M. Guttag ,  Donald J. Redwine

IPC: G09G5/36 ,  G06F12/00 ,  G09G5/00 ,  G09G5/39 ,  G09G5/395 ,  G11C7/10 ,  G11C11/401 ,  H04N5/907 ,  G11C8/00

CPC classification number: H04N5/907 ,  G11C7/1075

Abstract: In a video computer system having a RAM chip with a shift register connected to its serial output terminal and actuated by a first clock circuit, a second different clock circuit is included to cause the data bit in the first stage of the register to also appear at the serial output terminal of the chip. Accordingly, signals from the first clock circuit will then sequentially transfer data bits from the shift register, to the output terminal of the RAM chip, without omitting or losing a clock cycle, or a portion thereof.

Abstract translation: 在具有RAM芯片的视频计算机系统中，移位寄存器连接到其串行输出端并被第一时钟电路驱动，包括第二不同时钟电路，以使寄存器的第一级中的数据位也出现在 芯片的串行输出端子。 因此，来自第一时钟电路的信号将顺序地将数据位从移位寄存器传送到RAM芯片的输出端，而不会省略或丢失时钟周期或其一部分。

公开(公告)号：US4457066A

公开(公告)日：1984-07-03

申请号：US197293

申请日：1980-10-15

Applicant: G. R. Mohan Rao ,  Donald J. Redwine

Inventor： G. R. Mohan Rao ,  Donald J. Redwine

IPC: H01L21/768 ,  H01L21/8242 ,  H01L21/28

CPC classification number: H01L27/10844 ,  H01L21/768

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word address lines and the bias lines for the capacitors are formed by metal strips. The gates of the access transistors and the capacitor gates are polysilicon. Metal-to-polysilicon contacts are made to connect the metal word lines to the polysilicon gates of the access transistors and to connect the metal bias lines to the capacitor gates.

Abstract translation: 一个晶体管类型的动态读/写存储单元由单电平多晶硅工艺制成，其中字地址线和用于电容器的偏置线由金属条形成。 存取晶体管和电容器栅极的栅极是多晶硅。 金属到多晶硅的接触是将金属字线连接到存取晶体管的多晶硅栅极，并将金属偏压线连接到电容器栅极。

公开(公告)号：US4031415A

公开(公告)日：1977-06-21

申请号：US624813

申请日：1975-10-22

Applicant: Donald J. Redwine ,  Norishisa Kitagawa

Inventor： Donald J. Redwine ,  Norishisa Kitagawa

IPC: G11C11/413 ,  G11C11/408 ,  G11C17/12 ,  H03K3/356 ,  H03K3/286 ,  G11C11/40 ,  H03K3/353 ,  H03K5/20

CPC classification number: G11C11/4082 ,  G11C17/12 ,  H03K3/356095

Abstract: Disclosed is an address buffer circuit for use in semiconductor memories or the like which are implemented in MOS integrated circuits. A cross-coupled differential pair of MOS transistors is used to detect an address input during a short time window, and internal address signals are generated from the state of the cross-coupled pair.

Abstract translation: 公开了在MOS集成电路中实现的用于半导体存储器等的地址缓冲电路。 MOS晶体管的交叉耦合差分对用于在短时间窗口期间检测地址输入，并且从交叉耦合对的状态产生内部地址信号。

公开(公告)号：US5510298A

公开(公告)日：1996-04-23

申请号：US304628

申请日：1994-09-12

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/48 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44 ,  H01L21/48

CPC classification number: H01L21/768 ,  H01L23/481 ,  H01L2924/0002

Abstract: An integrated circuit interconnect structure is provided, along with a method of forming the integrated circuit interconnect structure. A semiconductor material layer has an elongate trench formed therein. A conducting region is disposed in the trench. An insulator region overlies the conducting region. One or more contact regions are disposed through the insulator region to contact the conducting region.

Abstract translation: 提供集成电路互连结构以及形成集成电路互连结构的方法。 半导体材料层具有形成在其中的细长沟槽。 导电区域设置在沟槽中。 绝缘体区域覆盖在导电区域上。 一个或多个接触区域穿过绝缘体区域设置以接触导电区域。

公开(公告)号：US5434969A

公开(公告)日：1995-07-18

申请号：US926721

申请日：1992-08-06

Applicant: Andrew L. Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

Inventor： Andrew L. Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

IPC: G11C7/10 ,  H04N5/907 ,  G06F12/06

CPC classification number: G11C7/1075 ,  H04N5/907

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a serial shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, a row of data is transferred into the serial shift register. Then the column address applied to the RAM unit is used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the serial shift register containing the data bits of interest.

Abstract translation: 在视频型计算机系统等中，提供了一种改进的存储器电路，用于使系统适应具有不同分辨率的CRT屏幕。 存储器电路包括具有足够的单元以适应任何想要使用的CRT屏幕的位映射RAM单元或芯片，以及具有对应于RAM单元中的不同列单元的多个不同位置的抽头的串行移位寄存器。 当RAM单元处于串行模式时，一行数据被传送到串行移位寄存器。 然后，应用于RAM单元的列地址用于指示和启动适当的解码器电路以选择适于卸载包含感兴趣的数据位的串行移位寄存器的部分的抽头。

公开(公告)号：US4989055A

公开(公告)日：1991-01-29

申请号：US366561

申请日：1989-06-15

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L27/108 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/108

Abstract: The described embodiments of the present invention provide a dynamic random access memory cell and array. The memory cell provides a three transistor storage device where the storage signal is stored on the gate of a storage transistor. All three transistors are integrated into a trench thereby providing the density equal to that of the densest of modern day DRAM cells. By using the three transistor concept, the first embodiment of the present invention provides a gain for the stored charge. Because the storage transistor amplifies the stored charge, the reduced capacitance of ultra-dense DRAM cells is overcome and adequate data sensing may be accomplished using capacitances much smaller than those useful in the single transistor, single capacitor DRAM cell.

Abstract translation: 本发明的所描述的实施例提供一种动态随机存取存储单元和阵列。 存储单元提供一个三晶体管存储器件，其中存储信号存储在存储晶体管的栅极上。 所有三个晶体管被集成到沟槽中，从而提供等于现代DRAM单元最密集密度的密度。 通过使用三晶体管的概念，本发明的第一实施例提供了存储电荷的增益。 由于存储晶体管放大存储的电荷，所以克服了超致密DRAM单元的降低的电容，并且可以使用比单晶体管单电容器DRAM单元中有用的电容更小的电容来实现足够的数据感测。

公开(公告)号：US4441246A

公开(公告)日：1984-04-10

申请号：US147433

申请日：1980-05-07

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  B01J17/00 ,  H01L21/306 ,  H01L27/04

CPC classification number: H01L27/1085 ,  H01L21/32105 ,  H01L27/10805

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by an improved process employing selective oxidation of polysilicon using PN junction capacitors. A relatively flat surface results from the process, which is favorable to patterning small geometries. The PN junction storage capacitors have improved alpha particle protection. Metal-to-polysilicon gate contacts are made at silicide areas over polysilicon gates; the silicide lowers resistance of the poly elements.

Abstract translation: 一个晶体管N沟道硅栅极型的动态读/写存储单元是通过使用PN结电容器选择性氧化多晶硅的改进工艺制成的。 相对平坦的表面由该方法产生，这有利于图案化的几何形状。 PN结储存电容器具有改进的α粒子保护。 金属到多晶硅栅极触点在多晶硅栅极的硅化物区域上制成; 硅化物降低了多元素的电阻。

公开(公告)号：US4330852A

公开(公告)日：1982-05-18

申请号：US97105

申请日：1979-11-23

Applicant: Donald J. Redwine ,  Lionel S. White, Jr. ,  G. R. Mohan Rao

Inventor： Donald J. Redwine ,  Lionel S. White, Jr. ,  G. R. Mohan Rao

IPC: G11C7/10 ,  G11C8/04 ,  G11C11/406 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C11/4096 ,  G11C11/406 ,  G11C7/1036 ,  G11C8/04

Abstract: A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.

Abstract translation: 使用动态单晶体管单元的MOS / LSI型半导体存储器件具有串行输入/输出系统。 具有等于​​存储单元阵列中的列数的级数的串行移位寄存器通过传输门连接到列。 寄存器中的位可以被加载到阵列的列中，并且因此被加载到寻址的单元行，或者一个整个寻址的单元行的数据可以经由列和传送门被加载到移位寄存器级。 来自外部的数据被串行地加载到移位寄存器用于写入操作，或者串行地从寄存器移出到外部用于读取操作。 在数据被移入或移出串行寄存器的时间期间，单元阵列可被寻址以进行刷新。