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    Memory device with internal signap processing unit
    11.
    发明授权
    Memory device with internal signap processing unit 有权
    具有内部封装处理单元的存储器件

    公开(公告)号：US08429493B2

    公开(公告)日：2013-04-23

    申请号：US12597494

    申请日：2008-04-16

    申请人： Dotan Sokolov ,  Naftali Sommer ,  Ofir Shalvi ,  Uri Perlmutter

    发明人： Dotan Sokolov ,  Naftali Sommer ,  Ofir Shalvi ,  Uri Perlmutter

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1072 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G11C11/56 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004

    摘要： A method for operating a memory (36) includes storing data in a plurality of analog memory cells (40) that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry (48) that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller (28), which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

    摘要翻译： 一种用于操作存储器（36）的方法包括：通过将输入存储值写入到一组模拟存储器单元中，将数据存储在制造在第一半导体管芯上的多个模拟存储单元（40）中。 在存储数据之后，使用相应的不同的阈值集合读取组中每个模拟存储器单元的多个输出存储值，从而提供分别对应于阈值集合的输出存储值的多个输出组。 输出存储值的多个输出组由在第一半导体管芯上制造的电路（48）预处理，以产生预处理的数据。 预处理数据被提供给存储器控制器（28），该存储器控制器（28）被制造在与第一半导体管芯不同的第二半导体管芯上，以使得存储器控制器可以响应于预处理的数据来重建数据。

    Selective Activation of Programming Schemes in Analog Memory Cell Arrays
    12.
    发明申请
    Selective Activation of Programming Schemes in Analog Memory Cell Arrays 有权
    模拟存储器单元阵列中编程方案的选择性激活

    公开(公告)号：US20120262971A1

    公开(公告)日：2012-10-18

    申请号：US13532714

    申请日：2012-06-25

    申请人： Dotan Sokolov ,  Naftali Sommer ,  Uri Perlmutter ,  Ofir Shalvi

    发明人： Dotan Sokolov ,  Naftali Sommer ,  Uri Perlmutter ,  Ofir Shalvi

    IPC分类号： G11C27/00

    CPC分类号： G11C27/005 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/3418

    摘要： A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

    摘要翻译： 一种用于数据存储的方法包括：定义第一编程方案，其编程一组模拟存储器单元，同时减少由与该组相邻的至少一个存储器单元引起的干扰;以及第二编程方案，其对该组模拟存储器单元进行编程 不能减少第一编程方案减少的所有干扰。 基于针对模拟存储器单元定义的标准来选择第一和第二编程方案之一。 使用所选择的编程方案将数据存储在模拟存储器单元的组中。

    Memory device with multiple-accuracy read commands
    13.
    发明授权
    Memory device with multiple-accuracy read commands 有权
    具有多重精度读取命令的存储器件

    公开(公告)号：US08059457B2

    公开(公告)日：2011-11-15

    申请号：US12405275

    申请日：2009-03-17

    申请人： Uri Perlmutter ,  Ofir Shalvi ,  Yoav Kasorla ,  Naftali Sommer ,  Dotan Sokolov

    发明人： Uri Perlmutter ,  Ofir Shalvi ,  Yoav Kasorla ,  Naftali Sommer ,  Dotan Sokolov

    IPC分类号： G11C11/34

    CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/349 ,  G11C27/005 ,  G11C29/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2211/5641

    摘要： A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command.

    摘要翻译： 一种用于数据存储的方法包括至少定义用于从模拟存储器单元读取存储值的第一和第二读取命令。 第一读取命令以第一精度读取存储值，并且第二读取命令以比第一精度更精细的第二精度读取存储值。 针对要在特定组的存储单元上执行的读取操作来评估条件。 响应于评估条件选择第一和第二读取命令中的一个。 使用所选择的读取命令从存储器单元的给定组中读取存储值。

    Selective Activation of Programming Schemes in Analog Memory Cell Arrays
    14.
    发明申请
    Selective Activation of Programming Schemes in Analog Memory Cell Arrays 有权
    模拟存储器单元阵列中编程方案的选择性激活

    公开(公告)号：US20100220509A1

    公开(公告)日：2010-09-02

    申请号：US12714501

    申请日：2010-02-28

    申请人： Dotan Sokolov ,  Naftali Sommer ,  Uri Perlmutter ,  Ofir Shalvi

    发明人： Dotan Sokolov ,  Naftali Sommer ,  Uri Perlmutter ,  Ofir Shalvi

    IPC分类号： G11C27/00 ,  G11C7/00

    CPC分类号： G11C27/005 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/3418

    摘要： A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

    摘要翻译： 一种用于数据存储的方法包括：定义第一编程方案，其编程一组模拟存储器单元，同时减少由与该组相邻的至少一个存储器单元引起的干扰;以及第二编程方案，其对该组模拟存储器单元进行编程 不能减少第一编程方案减少的所有干扰。 基于针对模拟存储器单元定义的标准来选择第一和第二编程方案之一。 使用所选择的编程方案将数据存储在模拟存储器单元的组中。

    STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N
    15.
    发明申请
    STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N 有权
    存储在N位/细胞模拟记忆体细胞中的位置/细胞密度M> N

    公开(公告)号：US20100124088A1

    公开(公告)日：2010-05-20

    申请号：US12618732

    申请日：2009-11-15

    申请人： Ofir Shalvi ,  Naftali Sommer ,  Uri Perlmutter ,  Dotan Sokolov

    发明人： Ofir Shalvi ,  Naftali Sommer ,  Uri Perlmutter ,  Dotan Sokolov

    IPC分类号： G11C27/00

    CPC分类号： G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C27/005 ,  G11C2211/5641

    摘要： A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.

    摘要翻译： 一种用于数据存储的方法包括接收用于存储在包括多个模拟存储器单元的存储器中的数据，并且支持一组内置的编程命令。 每个编程命令在存储器单元的子集中编写从一组N页中选择的相应页面。 存储器单元的子集被编程为通过执行仅从集合中绘制的编程命令的序列来存储数据的M页M> N。

    Programming Schemes for Multi-Level Analog Memory Cells
    17.
    发明申请
    Programming Schemes for Multi-Level Analog Memory Cells 有权
    多级模拟存储单元的编程方案

    公开(公告)号：US20120297270A1

    公开(公告)日：2012-11-22

    申请号：US13566372

    申请日：2012-08-03

    申请人： Ofir Shalvi ,  Naftali Sommer ,  Dotan Sokolov ,  Yoav Kasoria

    发明人： Ofir Shalvi ,  Naftali Sommer ,  Dotan Sokolov ,  Yoav Kasoria

    IPC分类号： G11C16/10 ,  G06F11/10 ,  H03M13/05

    CPC分类号： G11C11/5628 ,  G06F11/1008 ,  G06F11/1068 ,  G11C11/56 ,  G11C16/34 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/52 ,  H03M13/2906

    摘要： A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

    摘要翻译： 一种用于数据存储的方法包括：通过对存储器单元进行编程来采用各自的第一编程级别，来将第一数据位在第一时间存储在一组多位模拟存储单元中。 第二数据位通过对存储器单元进行编程以采取依赖于第一编程电平和第二数据位的相应的第二编程电平而在比第一时间晚的第二时间存储在存储单元组中。 响应于第一次和第二次之间的差异选择存储策略。 将存储策略应用于从第一数据位和第二数据位中选择的至少一组数据位。

    Reading memory cells using multiple thresholds
    18.
    发明授权
    Reading memory cells using multiple thresholds 有权
    使用多个阈值读取存储单元

    公开(公告)号：US07975192B2

    公开(公告)日：2011-07-05

    申请号：US11995814

    申请日：2007-10-30

    申请人： Naftali Sommer ,  Ofir Shalvi ,  Dotan Sokolov

    发明人： Naftali Sommer ,  Ofir Shalvi ,  Dotan Sokolov

    IPC分类号： G11C29/42 ,  G11C29/50

    CPC分类号： G06F11/1068 ,  G11C8/20 ,  G11C11/56 ,  G11C11/5642 ,  G11C27/005

    摘要： A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

    摘要翻译： 一种用于操作存储器（28）的方法包括：通过将从一组标称值中选择的相应模拟输入值写入到存储器的模拟存储器单元（32）中来存储用错误校正码（ECC）编码的数据， 模拟存储单元。 通过执行将模拟存储器单元的模拟输出值与不同的相应读取阈值进行比较的多个读取操作来读取存储的数据，以便为每个模拟存储器单元产生多个比较结果。 读取阈值中的至少两个位于在标称值的集合中彼此相邻的一对标称值之间。 响应于多个比较结果计算软指标。 使用软指标对ECC进行解码，以便提取存储在模拟存储单元中的数据。

    DATA STORAGE WITH INCREMENTAL REDUNDANCY
    19.
    发明申请
    DATA STORAGE WITH INCREMENTAL REDUNDANCY 有权
    数据存储与增量冗余

    公开(公告)号：US20080282106A1

    公开(公告)日：2008-11-13

    申请号：US12119069

    申请日：2008-05-12

    申请人： Ofir Shalvi ,  Dotan Sokolov ,  Eyal Gurgi ,  Oren Golov ,  Naftali Sommer

    发明人： Ofir Shalvi ,  Dotan Sokolov ,  Eyal Gurgi ,  Oren Golov ,  Naftali Sommer

    IPC分类号： G06F11/16

    CPC分类号： G06F11/1068 ,  G11C2029/0411

    摘要： A method for operating a memory includes encoding input data with an Error Correction Code (ECC) to produce input encoded data including first and second sections, such that the ECC is decodable based on the first section at a first redundancy, and based on both the first and the second sections at a second redundancy that is higher than the first redundancy.Output encoded data is read and a condition is evaluated. The input data is reconstructed using a decoding level selected, responsively to the condition, from a first level, at which a first part of the output encoded data corresponding to the first section is processed to decode the ECC at the first redundancy, and a second level, at which the first part and a second part of the output encoded data corresponding to the second section are processed jointly to decode the ECC at the second redundancy.

    摘要翻译： 一种用于操作存储器的方法包括用错误校正码（ECC）编码输入数据以产生包括第一和第二部分的输入编码数据，使得基于第一冗余部分的第一部分可以解码ECC，并且基于两者 第一和第二部分具有高于第一冗余的第二冗余。 读取输出编码数据并评估条件。 输入数据使用从第一级别选择的解码级别来重构，在第一级别处理对应于第一部分的输出编码数据的第一部分被处理以在第一冗余处解码ECC，以及第二级 级别，其中对应于第二部分的输出编码数据的第一部分和第二部分共同处理，以在第二冗余处对ECC进行解码。