公开(公告)号：US5216281A

公开(公告)日：1993-06-01

申请号：US750098

申请日：1991-08-26

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L21/76897 ,  H01L21/28512 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002

摘要： In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode A remnant (60a) of a doped silicon layer overlies the S/D and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. The doped silicon acting as a dopant for the source/drain region. A nitride, preferably Si.sub.3 N.sub.4, is located under the thick dielectric and over part of the gate electrode insulation. The Si.sub.3 N.sub.4 adjoins the doped silicon to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by the doped silicon at some locations and by the nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si.sub.3 N.sub.4 but not the doped silicon. The doped silicon is effective as a dry etch stop and a wet etch stop, and the silicon nitride is effective as an isotropic etch stop. The doped silicon is wholly contained within the contact, and the nitride extends beyond said contact.

摘要翻译： 在与栅电极（22）附近的源极/漏极区（28）的接触结构中，通过厚电介质的接触侧壁横向移位远离S / D区域以扩大触点; 接触侧壁位于栅电极A上方，掺杂硅层的残留物（60a）覆盖在S / D上，并且沿着栅电极绝缘体的侧壁上升并且上升到栅电极顶部的绝缘体上，从而与栅电极绝缘 。 掺杂硅充当源/漏区的掺杂剂。 氮化物，优选Si 3 N 4，位于厚电介质和栅电极绝缘体的一部分之下。 Si3N4与掺杂硅相邻，以氮化物包围栅电极的顶部和侧面。 接触的底部由一些位置处的掺杂硅和其它位置处的氮化物形成。 通过厚电介质的接触侧壁优选覆​​盖Si 3 N 4而不是掺杂的硅。 掺杂硅作为干蚀刻停止和湿蚀刻停止是有效的，并且氮化硅作为各向同性蚀刻停止是有效的。 掺杂硅完全包含在触点内，并且氮化物延伸超过所述触点。

公开(公告)号：US4893272A

公开(公告)日：1990-01-09

申请号：US184996

申请日：1988-04-22

申请人： S. Sheffield Eaton, Jr. ,  Douglas Butler ,  Michael Parris

发明人： S. Sheffield Eaton, Jr. ,  Douglas Butler ,  Michael Parris

IPC分类号： G11C11/41 ,  G11C11/22 ,  G11C14/00 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22

摘要： Polarization retention of a ferroelectric material in a memory cell is improved by open circuiting the write pulse. The depolarizing field is reduced by allowing charge to dissipate through the ferroelectric material, causing a polarizing field.

公开(公告)号：US07949257B2

公开(公告)日：2011-05-24

申请号：US11938754

申请日：2007-11-12

申请人： Christopher Lin ,  Mark Summa ,  Martin Williams ,  Douglas Butler ,  Peter Wigley

发明人： Christopher Lin ,  Mark Summa ,  Martin Williams ,  Douglas Butler ,  Peter Wigley

IPC分类号： H04B10/08 ,  H04B10/12 ,  H04B10/00 ,  H04J14/02

CPC分类号： H04B10/2513

摘要： One embodiment sets forth a technique for measuring chromatic dispersion using reference signals within the operational range of amplifiers used to refresh data signals. One red/blue laser pair in the transmission node is used for measuring dispersion and chromatic dispersion compensation is added at each line node in the system. Since reference and data signals propagate through each amplifier, the reference signals used to measure chromatic dispersion receive the same dispersion compensation (and will have the same residual dispersion) as the data signals. Therefore, any residual dispersion in the data signals will manifest itself in downstream dispersion measurements and, thus, can be corrected. The tunable dispersion compensator in each line node may be set to compensate for the measured dispersion, thereby compensating for both the chromatic dispersion of the link connecting the current node to the prior node and any uncorrected residual dispersion from prior nodes.

摘要翻译： 一个实施例提出了使用用于刷新数据信号的放大器的操作范围内的参考信号来测量色散的技术。 传输节点中的一个红/蓝激光对用于测量色散，并且在系统中的每个线路节点处添加色散补偿。 由于参考和数据信号通过每个放大器传播，用于测量色散的参考信号将接收与数据信号相同的色散补偿（并将具有相同的残留色散）。 因此，数据信号中的任何残留色散将在下游色散测量中显现，因此可以被校正。 每个线路节点中的可调谐色散补偿器可以被设置为补偿测量的色散，由此补偿连接当前节点到先前节点的链路的色散和来自先前节点的任何未校正的残余色散。

公开(公告)号：US20070176650A1

公开(公告)日：2007-08-02

申请号：US11687605

申请日：2007-03-16

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： H03B1/00

CPC分类号： G11C7/1078 ,  G11C7/1084

摘要： A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

摘要翻译： 用于集成电路器件的高速，低功耗输入缓冲器，其中输入电压（VIN）耦合到上拉和下拉晶体管。 根据具体实施例，输入缓冲器在操作的校准阶段期间利用参考电压输入（VREF），但在主动操作模式中不使用输入缓冲器。 当VIN = VREF时，在所有其他VIN电压下具有较低的通过电流电平时，提供最大电流通过电流。 在包含所公开的输入缓冲器的集成电路装置中，每个器件输入引脚可以使用两个（或多个）输入缓冲器。

公开(公告)号：US20070085152A1

公开(公告)日：2007-04-19

申请号：US11250822

申请日：2005-10-14

申请人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

发明人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC分类号： H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

摘要翻译： 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

公开(公告)号：US20060229839A1

公开(公告)日：2006-10-12

申请号：US11092175

申请日：2005-03-29

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： G01K1/00 ,  G01K3/00

CPC分类号： G01K3/005 ,  G01K7/01

摘要： A temperature sensing and monitoring technique for integrated circuit devices, particularly dynamic random access memory (DRAM), which incorporates the comparison of a voltage inversely proportional to temperature to a voltage proportional to temperature thereby increasing the differential voltage vs. temperature. In a representative embodiment disclosed herein, these two voltages are designed to be equal at a given temperature and a comparison circuit produces a signal that changes from a logic level “high” to a logic level “low” at that given temperature. An additional transistor in each trip point current path forces the gate-to-source and drain-to-source voltage of current mirror transistors to be equal at the temperature trip points.

摘要翻译： 用于集成电路装置，特别是动态随机存取存储器（DRAM）的温度感测和监测技术，其包括与温度成反比的电压与与温度成比例的电压的比较，从而增加差分电压对温度。 在本文公开的代表性实施例中，这两个电压被设计为在给定温度下相等，并且比较电路产生在该给定温度下从逻辑电平“高”变为逻辑电平“低”的信号。 每个跳变点电流路径中的附加晶体管迫使电流镜晶体管的栅极至源极和源极间电压在温度跳变点处相等。

公开(公告)号：US20060190678A1

公开(公告)日：2006-08-24

申请号：US11062974

申请日：2005-02-22

申请人： Douglas Butler ,  Oscar Jones ,  Michael Parris

发明人： Douglas Butler ,  Oscar Jones ,  Michael Parris

IPC分类号： G06F13/28

CPC分类号： G06F12/0893 ,  G06F2212/3042 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/40615 ,  G11C11/40618

摘要： A static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag provides a memory architecture comprising low cost DRAM memory cells that is available for system accesses 100% of the time and is capable of executing refreshes frequently enough to prevent data loss. Any subarray of the memory can be written from cache or refreshed at the same time any other subarray is read or written externally.

摘要翻译： 兼容的静态随机存取存储器（SRAM），高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）与单个DRAM高速缓存和标签相结合的方法提供了包括可用于系统访问的低成本DRAM存储器单元的存储器架构 100％的时间，并且能够频繁地执行刷新以防止数据丢失。 存储器的任何子阵列可以从高速缓存中写入或刷新，同时任何其他子阵列被外部读取或写入。

公开(公告)号：US20050286291A1

公开(公告)日：2005-12-29

申请号：US10878800

申请日：2004-06-28

申请人： Michael Parris ,  Oscar Jones ,  Douglas Butler

发明人： Michael Parris ,  Oscar Jones ,  Douglas Butler

IPC分类号： G11C7/10 ,  G11C11/24 ,  G11C11/4093

CPC分类号： G11C7/1048 ,  G11C7/1075 ,  G11C11/4093 ,  G11C2207/002

摘要： A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.

摘要翻译： 双存取DRAM包括第一和第二组数据线。 通过将第二组复用晶体管添加到与现有的多路复用晶体管类似的定时和寻址控制的数据线上，可以通过额外的一组数据线将数据传输到第二子阵列。 第二组数据线是除了正常的数据线之外使用的附加内部读/写线。 第二组数据线被设计为具有相应低电容的短长度，使得读出放大器上的额外负载较小。

公开(公告)号：US20050052219A1

公开(公告)日：2005-03-10

申请号：US10918954

申请日：2004-08-16

申请人： Douglas Butler ,  Kim Hardee

发明人： Douglas Butler ,  Kim Hardee

IPC分类号： H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H03K17/30 ,  H03K19/094 ,  G05F1/10

CPC分类号： G05F3/205

摘要： An integrated circuit transistor body bias regulation circuit and method of especial applicability with respect to low voltage applications wherein the threshold voltage (Vt) of certain transistors is lowered at low power supply voltage (VCC) levels, low temperature and/or high Vt process conditions to assure adequate transistor drive but may also be raised at high VCC levels, high temperature and/or low Vt process conditions to reduce leakage current. In this manner, circuit speed that is closer to constant (versus VCC, temperature and process variation) is thereby achieved.

摘要翻译： 一种集成电路晶体管体偏置调节电路及其在低电压应用中特别适用的方法，其中某些晶体管的阈值电压（Vt）在低电源电压（VCC）电平，低温和/或高Vt工艺条件下降低 以确保足够的晶体管驱动，但也可以在高VCC电平，高温和/或低Vt工艺条件下升高，以减少泄漏电流。 以这种方式，由此实现更接近恒定的电路速度（相对于VCC，温度和工艺变化）。