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    Semiconductor device comprising a contact structure based on copper and tungsten
    12.
    发明授权
    Semiconductor device comprising a contact structure based on copper and tungsten 有权
    包括基于铜和钨的接触结构的半导体器件

    公开(公告)号：US07902581B2

    公开(公告)日：2011-03-08

    申请号：US11428611

    申请日：2006-07-05

    申请人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

    发明人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

    IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing contact plugs having a lower plug portion, formed on the basis of well-established tungsten-based technologies, and an upper plug portion, which may comprise a highly conductive material such as copper or a copper alloy, a significant increase in conductivity of the contact structure may be achieved. For this purpose, after the deposition of a first dielectric layer of the inter-layer stack, a planarization process may be performed so as to allow the formation of the lower plug portions on the basis of tungsten, while, after the deposition of the second dielectric layer, a corresponding copper-based technology may be used for forming the upper plug portions of significantly enhanced conductivity.

    摘要翻译： 通过提供具有基于已经确定的钨基技术形成的下部插塞部分的接触插塞和可包括诸如铜或铜合金的高导电材料的上部插塞部分，导电性的显着增加 可以实现接触结构。 为此，在沉积层间堆叠的第一介电层之后，可以进行平面化处理，以便允许基于钨形成下部塞子部分，而在沉积第二层 电介质层，可以使用相应的铜基技术来形成具有显着增强的导电性的上部插塞部分。

    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL
    13.
    发明申请
    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL 有权
    用于补偿中间层介质材料中沉积行为差异的技术

    公开(公告)号：US20100285668A1

    公开(公告)日：2010-11-11

    申请号：US12841313

    申请日：2010-07-22

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/311 ,  H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS
    14.
    发明申请
    DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS 审中-公开
    低电阻金属层的双重整合方案

    公开(公告)号：US20090108462A1

    公开(公告)日：2009-04-30

    申请号：US12104692

    申请日：2008-04-17

    申请人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

    发明人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L23/53295 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density.

    摘要翻译： 通过在电阻敏感的金属化层中形成延伸穿过整个层间电介质材料的金属线，可获得这些金属化层的均匀性。 相应过孔开口的图案化可以基于形成在盖层中的凹槽来实现，该凹槽在沟槽图案化期间另外充当有效的蚀刻停止层，其延伸穿过整个层间电介质材料。 因此，对于电阻敏感金属化层中金属线的给定设计宽度，可以获得具有高程度均匀性的金属线的最大横截面积，而与通孔密度的变化无关。

    Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines
    18.
    发明授权
    Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines 有权
    在包括紧密间隔的线的结构之上形成可靠性高的层间电介质材料的技术

    公开(公告)号：US07910496B2

    公开(公告)日：2011-03-22

    申请号：US12020234

    申请日：2008-01-25

    申请人： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

    发明人： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76832 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

    摘要： By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.

    摘要翻译： 通过去除通过SACVD沉积的层间电介质材料的多余材料，可以利用该沉积技术的间隙填充能力，而另一方面可能降低该材料的负面影响。 在其它方面，可以在基于SACVD沉积层间电介质材料之前形成诸如二氧化硅的缓冲材料，从而当在具有不同高度固有的电介质层上沉积层间电介质材料时在沉积过程中产生增强的均匀性 压力水平。 因此，可以提高层间绝缘材料的可靠性，同时保持由SACVD沉积提供的优点。

    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material
    20.
    发明授权
    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material 有权
    补偿层间电介质材料沉积行为差异的技术

    公开(公告)号：US07785956B2

    公开(公告)日：2010-08-31

    申请号：US12168443

    申请日：2008-07-07

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。