利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

119 条记录 (耗时 0.022 秒)

    DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS
    2.
    发明申请
    DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS 审中-公开
    低电阻金属层的双重整合方案

    公开(公告)号：US20090108462A1

    公开(公告)日：2009-04-30

    申请号：US12104692

    申请日：2008-04-17

    申请人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

    发明人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L23/53295 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density.

    摘要翻译： 通过在电阻敏感的金属化层中形成延伸穿过整个层间电介质材料的金属线，可获得这些金属化层的均匀性。 相应过孔开口的图案化可以基于形成在盖层中的凹槽来实现，该凹槽在沟槽图案化期间另外充当有效的蚀刻停止层，其延伸穿过整个层间电介质材料。 因此，对于电阻敏感金属化层中金属线的给定设计宽度，可以获得具有高程度均匀性的金属线的最大横截面积，而与通孔密度的变化无关。

    Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines
    3.
    发明授权
    Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines 有权
    在包括紧密间隔的线的结构之上形成可靠性高的层间电介质材料的技术

    公开(公告)号：US07910496B2

    公开(公告)日：2011-03-22

    申请号：US12020234

    申请日：2008-01-25

    申请人： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

    发明人： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76832 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

    摘要： By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.

    摘要翻译： 通过去除通过SACVD沉积的层间电介质材料的多余材料，可以利用该沉积技术的间隙填充能力，而另一方面可能降低该材料的负面影响。 在其它方面，可以在基于SACVD沉积层间电介质材料之前形成诸如二氧化硅的缓冲材料，从而当在具有不同高度固有的电介质层上沉积层间电介质材料时在沉积过程中产生增强的均匀性 压力水平。 因此，可以提高层间绝缘材料的可靠性，同时保持由SACVD沉积提供的优点。

    TECHNIQUE FOR FORMING AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES
    4.
    发明申请
    TECHNIQUE FOR FORMING AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES 有权
    形成中间层介质材料的技术在包括封闭空间线的结构之上增加的可靠性

    公开(公告)号：US20090001526A1

    公开(公告)日：2009-01-01

    申请号：US12020234

    申请日：2008-01-25

    申请人： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

    发明人： Frank Feustel ,  Kai Frohberg ,  Carsten Peters

    IPC分类号： H01L21/31 ,  H01L23/58

    CPC分类号： H01L21/76832 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843

    摘要： By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.

    摘要翻译： 通过去除通过SACVD沉积的层间电介质材料的多余材料，可以利用该沉积技术的间隙填充能力，而另一方面可能降低该材料的负面影响。 在其它方面，可以在基于SACVD沉积层间电介质材料之前形成诸如二氧化硅的缓冲材料，从而当在具有不同高度固有的电介质层上沉积层间电介质材料时在沉积过程中产生增强的均匀性 压力水平。 因此，可以提高层间绝缘材料的可靠性，同时保持由SACVD沉积提供的优点。

    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER
    5.
    发明申请
    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER 审中-公开
    采用拉伸应力覆盖层的替代浇口方法中的超级填充条件

    公开(公告)号：US20120223388A1

    公开(公告)日：2012-09-06

    申请号：US13471818

    申请日：2012-05-15

    申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823807 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7843

    摘要： In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

    摘要翻译： 在用于在半导体器件中形成高k金属栅电极的替代栅极方法中，栅极开口的锥形配置可以通过使用横向邻近栅电极结构设置的拉应力电介质材料来实现。 因此，可以实现优异的沉积条件，同时可以有效地将拉伸应力分量用于一种类型的晶体管中的应变工程。 此外，可以在提供替换栅电极结构之后施加附加的压缩应力介电材料。

    SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE
    6.
    发明申请
    SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE 审中-公开
    通过半导体器件的隔离结构封装的自对准接触结构

    公开(公告)号：US20120021581A1

    公开(公告)日：2012-01-26

    申请号：US13237268

    申请日：2011-09-20

    申请人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    发明人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/76232

    摘要： By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.

    摘要翻译： 通过形成在由有源区的半导体材料限定的高度水平之上延伸的隔离结构，相应的凹槽可以与完成基本晶体管结构的栅电极结构相结合。 这些凹部可以随后用适当的接触材料填充，从而以自对准的方式形成大面积的接触，而不需要层间绝缘材料的沉积和图案化。 此后，例如，可以基于公知的技术形成第一金属化层，其中金属线可以直接连接到相应的“大面积”接触元件。