公开(公告)号：US20090109778A1

公开(公告)日：2009-04-30

申请号：US12108206

申请日：2008-04-23

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C7/06

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: In one embodiment, a sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell is provided. The sense amplifier includes: a first pair of switches including a first switch coupled to a node on the bit line and a second switch coupled to a node on the complementary bit line; a signal detector having a first input terminal coupled to the first switch and a second input terminal coupled to the second switch, the signal detector configured to sense voltages on the bit line and the complementary bit line through the first pair of switches during a read operation; a second pair of switches, wherein a first switch in the second pair couples between the node on the bit line and ground and is responsive to a data signal to be written to the memory cell and a second switch couples between the node on the complementary bit line and ground and is responsive to a complementary data signal to be written to the memory cell, wherein if either the data signal or the complementary data signal is true, a corresponding bit line is grounded so as to force the binary state of memory cell into an appropriate value during a write operation; and wherein the first pair of switches are controlled such that they turn on during a read operation while the signal detector determines the binary state of the memory cell, the first pair of switches being off during the write operation whereby a capacitance presented to the bit line and the complementary bit line by the sense amplifier is lower during the write operation than during the read operation.

Abstract translation: 在一个实施例中，提供了用于感测耦合到位线和互补位线并用于将二进制状态写入存储器单元的存储器单元的二进制状态的读出放大器。 读出放大器包括：第一对开关，包括耦合到位线上的节点的第一开关和耦合到互补位线上的节点的第二开关; 信号检测器，具有耦合到第一开关的第一输入端和耦合到第二开关的第二输入端，信号检测器被配置为在读取操作期间通过第一对开关检测位线上的电压和互补位线 ; 第二对开关，其中第二对中的第一开关在位线和地之间的节点之间耦合，并且响应于要写入存储器单元的数据信号，并且第二开关在互补位上的节点之间耦合 线和接地，并响应于要写入存储单元的互补数据信号，其中如果数据信号或互补数据信号为真，则相应的位线接地，以便将存储器单元的二进制状态 在写操作期间的适当值; 并且其中第一对开关被控制使得它们在读取操作期间它们导通，同时信号检测器确定存储器单元的二进制状态，第一对开关在写入操作期间关断，由此提供给位线的电容 并且读写放大器的互补位线在写操作期间比在读操作期间更低。

公开(公告)号：US07498838B2

公开(公告)日：2009-03-03

申请号：US11447495

申请日：2006-06-06

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: H03K19/173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件元件的可编程保险丝与多个存储器单元一起被使用以指示至少一个存储器单元不可用并且应该被移出而不工作。 软件可编程元件包括可编程寄存器，其适于移位指示至少一个存储器单元有缺陷的适当值。 硬件元件包括一个带可编程寄存器的保险丝。 移位由软件可编程保险丝或硬保险丝指示。 软熔丝寄存器可以链接在一起形成移位寄存器。

公开(公告)号：US07271615B2

公开(公告)日：2007-09-18

申请号：US11301236

申请日：2005-12-12

Applicant: Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

Inventor： Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/0016

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract translation: 在一个实施例中，NMOS晶体管的源极耦合到公共源节点，使得如果公共源节点接地，则NMOS晶体管导通泄漏电流。 为了减少漏电流，公共源节点处于潜在状态。 类似地，PMOS晶体管的源极耦合到公共源节点，使得如果公共源节点被充电到电源电压VDD，则PMOS晶体管传导泄漏电流。 为了减少漏电流，公共源节点的电位降低。

公开(公告)号：US07251159B2

公开(公告)日：2007-07-31

申请号：US11031445

申请日：2005-01-07

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C11/34

CPC classification number: G11C11/4125 ,  G11C11/412

Abstract: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to a second voltage level. In one embodiment, the first voltage level and the second voltage level are of opposite polarity. In one embodiment, to store a data bit having the value “0,” the first memory cell is set to a first voltage level and the second memory cell is set to a second voltage level of opposite polarity to the first voltage level, and to store a data bit having the value “1,” the first memory cell is set to a third voltage level and the second memory cell is set to a fourth voltage level of opposite polarity to the third voltage level. In an illustrative embodiment, the first voltage level is of substantially equal magnitude, and of opposite polarity, to the second voltage level, the third voltage level is of substantially equal magnitude, and of opposite polarity, to the fourth voltage level, the first voltage level is substantially equal to the fourth voltage level, and the second voltage level is substantially equal to the third voltage level. In one embodiment, the data stored according to the present invention is read out by comparing the relative voltages of the first and second memory cells with a differential sense amplifier.

Abstract translation: 用于实现强大的非易失性存储器的数据编码系统和方法。 使用两个存储单元存储数据位。 通过将第一存储器单元的电压电平设置为第一电压电平并将第二存储器单元的电压电平设置为第二电压电平来表示数据位。 在一个实施例中，第一电压电平和第二电压电平具有相反的极性。 在一个实施例中，为了存储具有值“0”的数据位，第一存储单元被设置为第一电压电平，并且第二存储单元被设置为与第一电压电平相反极性的第二电压电平，并且 存储具有值“1”的数据位，将第一存储单元设置为第三电压电平，将第二存储单元设置为与第三电压电平相反极性的第四电压电平。 在说明性实施例中，第一电压电平具有与第二电压电平基本相等的极性并且具有与第二电压电平相反的极性，第三电压电平基本相等于第四电压电平，并且具有与第四电压电平相反的极性 电平基本上等于第四电压电平，第二电压电平基本上等于第三电压电平。 在一个实施例中，通过将第一和第二存储器单元的相对电压与差分读出放大器进行比较来读出根据本发明存储的数据。

公开(公告)号：US20070109886A1

公开(公告)日：2007-05-17

申请号：US11616573

申请日：2006-12-27

Applicant: Esin Terzioglu ,  Gil Winograd ,  Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil Winograd ,  Cyrus Afghahi

IPC: G11C29/00

CPC classification number: G11C29/81 ,  G06F13/4086 ,  G11C7/06 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract translation: 本发明涉及一种通过替换这种存储器中的小块来提供分层存储器中的冗余的系统和方法。 本发明通过移位预编码线路或者在本地预解码器块中使用修改的移位预解码器电路来提供这种冗余（即，替代这样的小块）。 在一个实施例中，分层存储器结构包括适于被移出使用的至少一个有源预解码器; 以及至少一个适于被移入使用的冗余预解码器。

公开(公告)号：US20070096161A1

公开(公告)日：2007-05-03

申请号：US11606118

申请日：2006-11-30

Applicant: Esin Terzioglu ,  Mehdi Hatamian ,  Ali Anvar

Inventor： Esin Terzioglu ,  Mehdi Hatamian ,  Ali Anvar

IPC: H01L27/148 ,  H01L29/768

CPC classification number: H04N5/235 ,  H04N5/243 ,  H04N5/361 ,  H04N5/3658 ,  H04N5/378

Abstract: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If so, then the pixel gain is adjusted to correct or compensate for the image distortion in the region. For example, the gain of the charging amplifier or operational amplifier can be adjusted to correct for saturation. This can be done in real-time since hardware is being tuned for the correction instead of software.

Abstract translation: 成像装置包括多个光电二极管，其作为在单个CMOS衬底上排列成多列的光学像素。 检查多个像素传感器或光电二极管的输出以确定一个像素或像素区域是否处于饱和状态。 如果是这样，则调整像素增益以校正或补偿该区域中的图像失真。 例如，可以调整充电放大器或运算放大器的增益以校正饱和。 这可以实时完成，因为硬件正在调整而不是软件。

公开(公告)号：US07177225B2

公开(公告)日：2007-02-13

申请号：US10729405

申请日：2003-12-05

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

IPC: G11C11/00

CPC classification number: G11C29/81 ,  G06F13/4086 ,  G11C7/06 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.

Abstract translation: 本发明涉及一种通过替换这种存储器中的小块来提供分层存储器中的冗余的系统和方法。 本发明通过移位预编码线路或者在本地预解码器块中使用修改的移位预解码器电路来提供这种冗余（即，替代这样的小块）。 在一个实施例中，分层存储器结构包括至少一个冗余预解码器，适于为适于被移出的多个预解码器的至少一个有效预解码器进行移位。

公开(公告)号：US07035163B2

公开(公告)日：2006-04-25

申请号：US11058154

申请日：2005-02-15

Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi

IPC: G11C8/00

CPC classification number: G11C7/06

Abstract: A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

公开(公告)号：US20050281108A1

公开(公告)日：2005-12-22

申请号：US11209866

申请日：2005-08-23

Applicant: Esin Terzioglu ,  Morteza Afghahi ,  Mehdi Hatamian

Inventor： Esin Terzioglu ,  Morteza Afghahi ,  Mehdi Hatamian

IPC: G11C7/06 ,  G11C7/00

CPC classification number: G11C7/06

Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n-1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

Abstract translation: 具有存储器单元的分层存储器结构，以及与存储器单元耦合以形成第一层存储器模块的读出放大器和解码器，以及随后的层通过具有（n-1）层的存储器模块形成，所述存储器模块与（n） - 层读出放大器和（n）层译码器。 还提供了具有采样保持基准的单端读出放大器和电荷共享限制摆幅驱动读出放大器; 异步复位解码器; 具有行冗余性的字线解码器; 具有由冗余控制器操作的冗余存储单元的冗余设备; 扩散复制延迟电路; 高精度延迟测量电路; 以及在数据总线上施加有限的电压摆幅的数据传输总线电路。 提供了用于在没有插入的预充电周期的写后读取操作的方法，并且提供了具有插入的预充电周期的写后写入操作，任一操作在少于一个存储器访问周期中完成。

公开(公告)号：US20050141325A1

公开(公告)日：2005-06-30

申请号：US11064218

申请日：2005-02-23

Applicant: Gil Winograd ,  Esin Terzioglu

Inventor： Gil Winograd ,  Esin Terzioglu

IPC: G06F13/40 ,  G11C7/18 ,  G11C11/419 ,  G11C29/00 ,  G11C8/00

CPC classification number: G11C29/808 ,  G06F13/4086 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/846 ,  G11C29/848

Abstract: The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.

Abstract translation: 本发明涉及适于增加存储器单元和存储器架构设计产量的系统和方法。 本发明包括具有解码器和多存储体存储器的存储器架构。 解码器适用于解码地址。 所述多存储体存储器与所述解码器交互，其中所述多存储体存储器包括适于完成所述多存储体存储器中的故障库的单词的至少一个输出数据位。