公开(公告)号：US20160344283A1

公开(公告)日：2016-11-24

申请号：US15159794

申请日：2016-05-19

Applicant: FSP TECHNOLOGY INC.

Inventor： Kuo-Fan Lin

IPC: H02M1/42 ,  H02M1/36 ,  H02M1/08 ,  H02M3/335

CPC classification number: H02M1/36 ,  H02M1/4225 ,  H02M3/33507 ,  H02M2001/007 ,  Y02B70/126 ,  Y02P80/112

Abstract: A management circuit for a power supply is provided. The power supply includes a power factor correction circuit and a power conversion circuit. An output of the power factor correction circuit is coupled to an input of the power conversion circuit. The management circuit includes a power factor correction controller, a pulse width modulation controller and a control circuit. The power factor correction controller controls power factor correction of the power factor correction circuit. The pulse width modulation controller controls power conversion of the power conversion circuit. The control circuit selectively activates the pulse width modulation controller according to a first activated signal generated by an input power of the power supply. After the pulse width modulation controller is activated, the control circuit generates a second activated signal based on the first activated signal. The control circuit activates the power factor conversion controller according to the second activated signal.

Abstract translation: 提供用于电源的管理电路。 电源包括功率因数校正电路和功率转换电路。 功率因数校正电路的输出耦合到功率转换电路的输入端。 管理电路包括功率因数校正控制器，脉宽调制控制器和控制电路。 功率因数校正控制器控制功率因数校正电路的功率因数校正。 脉宽调制控制器控制电源转换电路的功率转换。 控制电路根据由电源的输入功率产生的第一激活信号选择性地激活脉宽调制控制器。 在脉宽调制控制器被激活之后，控制电路基于第一激活信号产生第二激活信号。 控制电路根据第二激活信号激活功率因数转换控制器。

公开(公告)号：US09455635B2

公开(公告)日：2016-09-27

申请号：US14465855

申请日：2014-08-22

Applicant: FSP TECHNOLOGY INC.

Inventor： Kuo-Fan Lin

IPC: H02M1/34 ,  H02M3/335

CPC classification number: H02M3/33507 ,  H02M3/335 ,  H02M2001/342 ,  H02M2001/344 ,  Y02B70/1491

Abstract: A snubber circuit includes a capacitor and a buffer device. The buffer device has a first terminal and a second terminal. The first terminal is electrically connected to the capacitor. When the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device. When the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal.

Abstract translation: 缓冲电路包括电容器和缓冲装置。 缓冲装置具有第一端子和第二端子。 第一端子电连接到电容器。 当缓冲器件以第一导通模式工作时，充电电流从第二端子通过缓冲器件流向第一端子。 当缓冲器件从第一导通模式切换到第二导通模式时，缓冲器件产生在特定时间段内通过缓冲器从第一端子流到第二端子的放电电流，使得在缓冲器件 进入第二导通模式，在第二端子处首先出现的相对最大电压电平低于第一端子处的电压电平。

公开(公告)号：US20150055262A1

公开(公告)日：2015-02-26

申请号：US14465855

申请日：2014-08-22

Applicant: FSP TECHNOLOGY INC.

Inventor： Kuo-Fan Lin

IPC: H02M1/34 ,  H02M3/335

CPC classification number: H02M3/33507 ,  H02M3/335 ,  H02M2001/342 ,  H02M2001/344 ,  Y02B70/1491

Abstract: A snubber circuit includes a capacitor and a buffer device. The buffer device has a first terminal and a second terminal. The first terminal is electrically connected to the capacitor. When the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device. When the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal.

Abstract translation: 缓冲电路包括电容器和缓冲装置。 缓冲装置具有第一端子和第二端子。 第一端子电连接到电容器。 当缓冲器件在第一导通模式下工作时，充电电流从第二端子通过缓冲器件流向第一端子。 当缓冲器件从第一导通模式切换到第二导通模式时，缓冲器件产生在特定时间段内通过缓冲器从第一端子流到第二端子的放电电流，使得在缓冲器件 进入第二导通模式，在第二端子处首先出现的相对最大电压电平低于第一端子处的电压电平。

公开(公告)号：US10256583B2

公开(公告)日：2019-04-09

申请号：US15202579

申请日：2016-07-06

Applicant: FSP TECHNOLOGY INC.

Inventor： Kuo-Fan Lin

IPC: H01R24/68 ,  H02M7/00 ,  H01R13/66 ,  H01R103/00 ,  H02M7/12

Abstract: A power adapter including a main circuit board and an auxiliary circuit board is provided. The main circuit board has a first surface and a second surface opposite to each other, and the first surface of the main circuit board is configured with a transformer and a first capacitor. The auxiliary circuit board has a first surface and a second surface opposite to each other, and the first surface of the auxiliary circuit board is configured with an input rectifier filter circuit, where the auxiliary circuit board is disposed in parallel above the main circuit board, and the input rectifier filter circuit of the auxiliary circuit board is electrically connected to the first capacitor of the main circuit board. Under a condition of same electrical parameters and dimensions, the volume of the power adapter of the invention is only a half of that of the existing power adapter, which satisfies a demand for miniaturization of the electronic devices.

公开(公告)号：US20160277017A1

公开(公告)日：2016-09-22

申请号：US15166236

申请日：2016-05-26

Applicant: FSP TECHNOLOGY INC.

Inventor： Kuo-Fan Lin

IPC: H03K17/081 ,  H01L21/56 ,  H02M1/34 ,  H01L23/00 ,  H01L23/31

CPC classification number: H03K17/08112 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49589 ,  H01L23/62 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/1703 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/4816 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12035 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3011 ,  H02M1/34 ,  H02M2001/344 ,  H03K17/08104 ,  H03K17/08116 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A snubber circuit is provided. The snubber circuit includes a transistor structure and a first capacitor. The transistor structure includes a chip package and two pins. The chip package includes a transistor die and a molding compound encapsulating the transistor die. A first pin of the two pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin of the two pins is electrically connected to a third bonding pad of the transistor die. The first pin or the second pin of the transistor structure is electrically connected to a terminal of the first capacitor.

Abstract translation: 提供缓冲电路。 缓冲电路包括晶体管结构和第一电容器。 晶体管结构包括芯片封装和两个引脚。 芯片封装包括晶体管管芯和封装晶体管管芯的模塑料。 两个引脚的第一引脚电连接到晶体管管芯的第一焊盘和第二接合焊盘，并且两个引脚的第二引脚电连接到晶体管管芯的第三焊盘。 晶体管结构的第一引脚或第二引脚电连接到第一电容器的端子。

公开(公告)号：US10600562B2

公开(公告)日：2020-03-24

申请号：US15464269

申请日：2017-03-20

Applicant: FSP TECHNOLOGY INC.

Inventor： Kuo-Fan Lin ,  Fu-Kai Tu

IPC: H01F27/34 ,  H01F3/14 ,  H01F17/04

Abstract: A manufacturing method of a magnetic element includes the following steps: forming a block including a central post and at least one lateral post with magneto-conductive materials; cutting the block along a first plane passing through the central and lateral posts to form a first half body and a second half body; combining the first half body with the second half body to form a first air gap between the central post of the first half body and the central post of the second half body and a second air gap between the lateral post of the first half body and the lateral post of the second half body; and cutting or grinding the combined first half body and second half body along a second plane passing through the central post and the lateral post to form a third half body including the first and second air gaps.

公开(公告)号：US20190097524A1

公开(公告)日：2019-03-28

申请号：US16199231

申请日：2018-11-26

Applicant: FSP TECHNOLOGY INC.

Inventor： Kuo-Fan Lin

IPC: H02M1/34 ,  H01L25/16 ,  H01L23/00

Abstract: A snubber circuit is provided. The snubber circuit includes a transistor structure and a first capacitor. The transistor structure includes a chip package and two pins. The chip package includes a transistor die and a molding compound encapsulating the transistor die. A first pin of the two pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin of the two pins is electrically connected to a third bonding pad of the transistor die. The first pin or the second pin of the transistor structure is electrically connected to a terminal of the first capacitor.