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公开(公告)号:US09722541B2
公开(公告)日:2017-08-01
申请号:US15045860
申请日:2016-02-17
Applicant: FUJITSU LIMITED
Inventor: Masaru Sato , Naoko Kurahashi
IPC: H03F3/60 , H03F1/02 , H03F1/18 , H03F1/42 , H03F3/193 , H03F3/195 , H03F3/72 , H03F1/56 , H03F1/07
CPC classification number: H03F1/0205 , H03F1/0288 , H03F1/07 , H03F1/18 , H03F1/42 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/604 , H03F3/607 , H03F3/72 , H03F2200/27 , H03F2200/315 , H03F2200/36 , H03F2200/42 , H03F2200/423 , H03F2200/451 , H03F2200/48 , H03F2200/519 , H03F2200/555 , H03F2200/75 , H03F2203/7227
Abstract: A distributed amplifier includes: an input-side transmission line; M amplification circuits; M output-side transmission lines; and a combination circuit configured to combine outputs of the M output-side transmission lines; wherein the input-side transmission line has an input-side serial line formed by connecting in series M×N unit transmission lines each including the same line length, and an input-side terminating resistor, the M amplification circuits each includes N amplifiers and the N amplifiers of the i-th amplification circuit take the input node of the ((k−1) M+i)-th input-side transmission line to be the input, and the output-side transmission line includes an output-side serial line including N transmission lines each being connected in series between the neighboring outputs of the N amplifiers and each having a line width in which the phase of the output of the amplifier in each stage agrees with one another.
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公开(公告)号:US09374065B2
公开(公告)日:2016-06-21
申请号:US14273990
申请日:2014-05-09
Applicant: FUJITSU LIMITED
Inventor: Masaru Sato
Abstract: A first transistor and a second transistor cascade-connected, a wiring which connects a drain of the first transistor and a gate of the second transistor, a capacitor whose one terminal is connected between the first transistor and the second transistor cascade-connected and whose other terminal is grounded, and a control circuit are included. The control circuit adjusts an inductance value by controlling a capacitance value of the capacitor or gate voltage of the first transistor or the second transistor.
Abstract translation: 连接第一晶体管的漏极和第二晶体管的栅极的第一晶体管和第二晶体管,一个端子连接在第一晶体管和第二晶体管级联连接的电容器,其另一个 端子接地,并且包括控制电路。 控制电路通过控制第一晶体管或第二晶体管的电容器的电容值或栅极电压来调整电感值。
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公开(公告)号:US09281790B2
公开(公告)日:2016-03-08
申请号:US14599639
申请日:2015-01-19
Applicant: FUJITSU LIMITED
Inventor: Masaru Sato
CPC classification number: H03F3/601 , H03F1/342 , H03F1/56 , H03F2200/405 , H03F2200/72
Abstract: An amplifier circuit has a plurality of amplifiers configured to be connected in series, and each of the plurality of amplifiers has an amplifying element configured to non-inverting amplify a signal and a phase adjustment element configured to be connected to an output terminal of the amplifying element and to adjust a phase of the signal, wherein the amplifying element is subjected to negative feedback, and wherein a stability coefficient of a circuit in which the amplifying elements of the number the same as the number of the plurality of amplifiers are connected in series is less than 1.
Abstract translation: 放大器电路具有被配置为串联连接的多个放大器,并且多个放大器中的每个放大器具有被配置为同相放大信号的放大元件和被配置为连接到放大器的输出端子的相位调整元件 并且调整所述信号的相位,其中所述放大元件经受负反馈,并且其中与所述多个放大器的数量相同的数量的放大元件串联连接的电路的稳定系数 小于1。
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公开(公告)号:US20140284804A1
公开(公告)日:2014-09-25
申请号:US14172020
申请日:2014-02-04
Applicant: FUJITSU LIMITED
Inventor: Toshihide Suzuki , Masaru Sato
IPC: H01L23/48
CPC classification number: H01L23/481 , H01L23/5223 , H01L23/5225 , H01L23/66 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a first electrode formed on a substrate, the first electrode being a first electrical potential; and a second electrode formed on the first electrode, the second electrode including a signal wiring that transmits a signal and a planar electrode part with a prescribed area. A shape of the first electrode corresponding to the planar electrode part is made into a slit shape such that a longitudinal direction of a slit is parallel to a direction in which the signal proceeds in the planar electrode part.
Abstract translation: 半导体器件包括形成在衬底上的第一电极,第一电极是第一电位; 以及形成在所述第一电极上的第二电极,所述第二电极包括发送信号的信号线和具有规定区域的平面电极部。 对应于平面电极部分的第一电极的形状被制成狭缝形状,使得狭缝的纵向方向平行于在平面电极部分中信号进行的方向。
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公开(公告)号:US11894867B2
公开(公告)日:2024-02-06
申请号:US17678611
申请日:2022-02-23
Applicant: FUJITSU LIMITED
Inventor: Masaru Sato
CPC classification number: H04B1/0458 , H04B1/0057 , H04B1/0483
Abstract: A transmission device includes a signal source configured to output a local signal with a first frequency, a first amplifier configured to amplify the local signal output from the signal source, a first mixer configured to mix a first input signal with an intermediate frequency and the local signal amplified by the first amplifier and to output a first output signal, and a second mixer configured to mix the first output signal output from the first mixer and the local signal amplified by the first amplifier and to output a second output signal.
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公开(公告)号:US10003313B2
公开(公告)日:2018-06-19
申请号:US15463452
申请日:2017-03-20
Applicant: FUJITSU LIMITED
Inventor: Masaru Sato
CPC classification number: H03F3/193 , H03F1/523 , H03F1/56 , H03F1/565 , H03F2200/18 , H03F2200/222 , H03F2200/294 , H03F2200/387 , H03F2200/465 , H03F2200/72
Abstract: An amplification circuit has a field effect transistor, an input side matching circuit, an output side matching circuit, a capacitor, and a resistor. The input side matching circuit is connected between an input port and the source terminal of the field effect transistor and outputs an input signal that changes with a bias voltage as a center value. The output side matching circuit is connected between an output port and the drain terminal of the field effect transistor. The capacitor is connected between the gate terminal of the field effect transistor and a first reference voltage source. The resistor is connected between the gate terminal of the field effect transistor and the first reference voltage source.
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公开(公告)号:US09054641B2
公开(公告)日:2015-06-09
申请号:US14029040
申请日:2013-09-17
Applicant: FUJITSU LIMITED
Inventor: Masaru Sato
Abstract: A variable phase shifter. The variable phase shifter includes: a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency; a synthesizer that includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports, and that on input of the input signal takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer.
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