公开(公告)号：US09287130B1

公开(公告)日：2016-03-15

申请号：US14676345

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Bruce Doris ,  Kangguo Cheng ,  Jason R. Cantone ,  Sylvie Mignot ,  David Moreau ,  Muthumanickam Sankarapandian ,  Pierre Morin ,  Su Chen Fan ,  Kisik Choi ,  Murat K. Akarvardar

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/66795

Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

Abstract translation: 一种方法包括在基底上形成多个翅片元件。 在基板上形成掩模。 掩模具有限定在多个翅片元件中的至少一个选定翅片元件上方的开口。 通过开口将离子物质注入到至少一个选定的翅片元件中，以相对于其它翅片元件增加其蚀刻特性。 选择性地将至少一个选定的翅片元件相对于其它翅片元件移除。

公开(公告)号：US20150294912A1

公开(公告)日：2015-10-15

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.