-
公开(公告)号:US20200159105A1
公开(公告)日:2020-05-21
申请号:US16191589
申请日:2018-11-15
Applicant: GLOBALFOUNDRIES INC.
Inventor: Jia Zeng , Guillaume Bouche , Lei Sun , Geng Han
IPC: G03F1/24 , H01L21/033 , H01L21/308 , H01L21/3213 , H01L21/311
Abstract: Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.
-
12.
公开(公告)号:US10651284B2
公开(公告)日:2020-05-12
申请号:US15791650
申请日:2017-10-24
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Ruilong Xie , Youngtag Woo , Daniel Chanemougame , Bipul C. Paul , Lars W. Liebmann , Heimanu Niebojewski , Xuelian Zhu , Lei Sun , Hui Zang
IPC: H01L29/49 , H01L27/092 , H01L29/78 , H01L21/28 , H01L29/66 , H01L29/417 , H01L21/8234 , H01L27/088
Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.
-
公开(公告)号:US20200004155A1
公开(公告)日:2020-01-02
申请号:US16022752
申请日:2018-06-29
Applicant: GLOBALFOUNDRIES INC.
Inventor: Yong Liang , Lei Sun , Yongan Xu , Craig D. Higgins
Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer. Movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer improves photoresist layer development and pattern resolution.
-
公开(公告)号:US20190271918A1
公开(公告)日:2019-09-05
申请号:US15909071
申请日:2018-03-01
Applicant: GLOBALFOUNDRIES INC.
Inventor: Lei Sun , Guoxiang Ning , Meixiong Zhao , Erfeng Ding
IPC: G03F7/20 , H01L21/308
Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.
-
公开(公告)号:US10332745B2
公开(公告)日:2019-06-25
申请号:US15597277
申请日:2017-05-17
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Lei Sun , Ruilong Xie , Wenhui Wang , Yulu Chen , Erik Verduijn , Zhengqing John Qi , Guoxiang Ning , Daniel J. Dechene
IPC: H01L21/027 , H01L21/033 , H01L21/768 , H01L21/3065
Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.
-
公开(公告)号:US20190148240A1
公开(公告)日:2019-05-16
申请号:US16243863
申请日:2019-01-09
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Ruilong Xie , Youngtag Woo , Daniel Chanemougame , Bipul C. Paul , Lars W. Liebmann , Heimanu Niebojewski , Xuelian Zhu , Lei Sun , Hui Zang
IPC: H01L21/8234 , H01L23/528 , H01L21/768 , H01L23/522 , H01L27/088
Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.
-
17.
公开(公告)号:US20190123162A1
公开(公告)日:2019-04-25
申请号:US15791650
申请日:2017-10-24
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Ruilong Xie , Youngtag Woo , Daniel Chanemougame , Bipul C. Paul , Lars W. Liebmann , Heimanu Niebojewski , Xuelian Zhu , Lei Sun , Hui Zang
IPC: H01L29/49 , H01L27/092 , H01L29/417 , H01L21/28 , H01L29/66 , H01L29/78
Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.
-
公开(公告)号:US20190056671A1
公开(公告)日:2019-02-21
申请号:US15681007
申请日:2017-08-18
Applicant: GLOBALFOUNDRIES INC.
Inventor: Lei Sun , John Zhang , Shao Beng Law , Guoxiang Ning , Xunyuan Zhang , Ruilong Xie
IPC: G03F7/20 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/544 , C23C14/22 , C23C16/455
Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.
-
19.
公开(公告)号:US20180286681A1
公开(公告)日:2018-10-04
申请号:US15478441
申请日:2017-04-04
Applicant: GLOBALFOUNDRIES INC.
Inventor: Erik A. Verduijn , Genevieve Beique , Nicholas V. LiCausi , Lei Sun , Francis G. Goodwin
IPC: H01L21/033 , H01L21/66
Abstract: The disclosure is directed to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space. One method may include: identifying a space between freestanding spacers as being one of: a former mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.
-
公开(公告)号:US10056291B2
公开(公告)日:2018-08-21
申请号:US15360255
申请日:2016-11-23
Applicant: GLOBALFOUNDRIES INC.
Inventor: Shao Beng Law , Xunyuan Zhang , Frank W. Mont , Genevieve Beique , Lei Sun
IPC: H01L21/4763 , H01L21/768 , H01L21/033 , H01L21/311 , H01L21/027 , H01L23/528 , H01L21/3205 , H01L21/285
CPC classification number: H01L21/76816
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.
-
-
-
-
-
-
-
-
-