公开(公告)号：US09023697B2

公开(公告)日：2015-05-05

申请号：US13962322

申请日：2013-08-08

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kevin K. Chan ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Min Yang ,  Qi Zhang

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.

Abstract translation: 形成半导体结构的方法包括在多个鳍片的暴露部分上生长外延掺杂层。 外延掺杂层将散热片的暴露部分组合以形成合并的源极和漏极区域。 通过外延掺杂层在鳍片中发生注入工艺，以改变鳍片的晶格以形成非晶化鳍片。 氮化物层沉积在半导体结构上。 氮化物层覆盖合并的源区和漏区。 在半导体结构中进行热处理以使非晶化翅片再结晶以形成再结晶的翅片。 再结晶的翅片，外延掺杂层和氮化物层形成应变源极和漏极区域，其对沟道区域引起应力。

公开(公告)号：US09236258B2

公开(公告)日：2016-01-12

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US09219002B2

公开(公告)日：2015-12-22

申请号：US14028724

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Richard J. Carter ,  Hongliang Shen ,  Daniel Pham ,  Sruthi Muralidharan

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。

公开(公告)号：US20150311081A1

公开(公告)日：2015-10-29

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US20150021695A1

公开(公告)日：2015-01-22

申请号：US13944048

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。