公开(公告)号：US09337323B2

公开(公告)日：2016-05-10

申请号：US14496430

申请日：2014-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： James S. Dunn ,  Qizhi Liu

IPC: H01L29/732 ,  G06F17/50 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/732 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 在衬底中形成第一隔离结构以限定器件区域的边界。 在器件区域中形成集电极，在器件区域形成第二隔离结构。 第二个隔离结构定义了收集器的边界。 第二隔离结构相对于第一隔离结构横向定位，以限定第一和第二隔离结构之间的器件区域的一部分。

公开(公告)号：US20160043202A1

公开(公告)日：2016-02-11

申请号：US14922457

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Qizhi Liu

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66287

Abstract: A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures.

Abstract translation: 集电极区域形成在衬底内的绝缘浅沟槽隔离区域之间。 在集电极区域和浅沟槽隔离区域外延生长基材。 基底材料在集电极区域形成基极区域，在浅沟槽隔离区域上形成非本征基极区域。 此外，牺牲发射极结构在基极区域上被图案化，并且在牺牲发射极结构上形成侧壁间隔物。 平面隆起的基底结构在基极区域和外部基极区域外延生长，凸起的基底结构的上层被氧化。 去除牺牲发射极结构以在侧壁间隔物之间​​留出开放空间，并且在侧壁间隔件之间的开放空间内形成发射体。 凸起的基部结构的上层包括将发射器与凸起的基部结构电绝缘的平面绝缘体。

公开(公告)号：US20200066885A1

公开(公告)日：2020-02-27

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

公开(公告)号：US10535551B2

公开(公告)日：2020-01-14

申请号：US15919744

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L21/762 ,  H01L27/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/868 ,  H01L29/872 ,  H01L29/16 ,  H01L29/161

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.

公开(公告)号：US20190252530A1

公开(公告)日：2019-08-15

申请号：US16394421

申请日：2019-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L29/08 ,  H01L23/535 ,  H01L27/12 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/535 ,  H01L27/04 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7371

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US10115810B2

公开(公告)日：2018-10-30

申请号：US15437168

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L21/331 ,  H01L29/66 ,  H01L29/737 ,  H01L29/165

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

公开(公告)号：US09608096B1

公开(公告)日：2017-03-28

申请号：US14874039

申请日：2015-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  David L. Harame

IPC: H01L29/49 ,  H01L29/732 ,  H01L21/762 ,  H01L29/66 ,  H01L21/225 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/732 ,  H01L21/76 ,  H01L21/762 ,  H01L29/0642 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.

公开(公告)号：US09576899B2

公开(公告)日：2017-02-21

申请号：US14746891

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Ian A. McCallum-Cook

IPC: H01L23/00 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5329

Abstract: Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region.

Abstract translation: 电熔丝和形成电熔丝的方法。 植入半导体衬底以限定半导体衬底中的改性区域。 围绕改性区域并且穿透到半导体衬底中的深度大于修饰区域的深度的沟槽形成在修改区域中，以便限定电熔丝的熔断体。 通过选择性蚀刻工艺从熔丝链下方去除衬底，其以比修改区域的第二蚀刻速率高的第一蚀刻速率去除半导体衬底。

公开(公告)号：US09570564B2

公开(公告)日：2017-02-14

申请号：US14451716

申请日：2014-08-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deborah A. Alperstein ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Keith J. Machia ,  Christa R. Willets

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 在包含第一端子的基板上形成第一半导体层。 在第一半导体层上形成蚀刻停止层，在蚀刻停止层上形成第二半导体层。 蚀刻第二半导体层以在第二半导体层上的蚀刻掩模的位置处限定第二端子。 选择包括蚀刻停止层的第一材料和包括第二半导体层的第二材料，使得第二半导体层的第二材料以比蚀刻停止层的第一材料更高的蚀刻速率蚀刻。 第一半导体层可以是用于形成双极结型晶体管的本征基极和非本征基极的基极层。

公开(公告)号：US09553145B2

公开(公告)日：2017-01-24

申请号：US14476007

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： David L. Harame ,  Michael L. Kerbaugh ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/732 ,  H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/1004 ,  H01L21/84 ,  H01L27/12 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/66272 ,  H01L29/732

Abstract: Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors.

Abstract translation: 形成双极器件结构和双极器件结构的方法。 可以在绝缘体上硅衬底的器件层中形成开口，该器件层延伸到绝缘体上硅衬底的掩埋绝缘体层。 内部基极层可以通过在与开口相邻的器件层的相对的第一和第二侧壁上的横向生长而在器件层内生长。 器件结构的第一双极结型晶体管的第一集电极可以以与第一侧壁隔开的第一间隔形成。 器件结构的第二双极结晶体管的第二集电极可以形成在距离第二侧壁的第二间隔处。 在开口内形成由第一双极结型晶体管和第二双极晶体管共用的发射极。 本征基极层的一部分可以为第一和第二双极结型晶体管提供相应的本征基极。