公开(公告)号：US10714591B2

公开(公告)日：2020-07-14

申请号：US16777243

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Hui Zang

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

Abstract: One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.

公开(公告)号：US10204861B2

公开(公告)日：2019-02-12

申请号：US15399200

申请日：2017-01-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xuelian Zhu ,  Jia Zeng ,  Wenhui Wang ,  Youngtag Woo ,  Jongwook Kye

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

公开(公告)号：US09437481B2

公开(公告)日：2016-09-06

申请号：US14674792

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jia Zeng ,  Youngtag Woo ,  Jongwook Kye

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/76802 ,  H01L21/027 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.

Abstract translation: 一种方法包括在硬掩模层之上形成心轴元件，在心轴元件上形成第一和第二间隔物，去除心轴元件，限定在第一和第二间隔物之间​​的第一开口，并暴露硬掩模层的一部分并具有 沿第一方向延伸的纵轴，形成覆盖所述第一开口的中间部分的阻挡掩模，所述阻挡掩模具有在与所述第一方向不同的第二方向上延伸的纵向轴线;在所述阻挡掩模的存在下， 阻挡掩模和所述第一和第二间隔物，以限定在所述硬掩模层中沿所述第一方向延伸的对准的第一和第二线段开口，基于所述第一和第二线段开口蚀刻设置在所述硬掩模层下方的电介质层中的凹陷， 并用导电材料填充凹部。

公开(公告)号：US10651284B2

公开(公告)日：2020-05-12

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US20190148240A1

公开(公告)日：2019-05-16

申请号：US16243863

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

公开(公告)号：US20190123162A1

公开(公告)日：2019-04-25

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US10109636B2

公开(公告)日：2018-10-23

申请号：US15453124

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Bipul C. Paul

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/3213 ,  H01L21/768

Abstract: A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.

公开(公告)号：US20180261604A1

公开(公告)日：2018-09-13

申请号：US15453124

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L27/1104 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207

Abstract: A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.

公开(公告)号：US09406775B1

公开(公告)日：2016-08-02

申请号：US14696684

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Youngtag Woo

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L27/11 ,  H01L21/768

CPC classification number: H01L29/66515 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a substrate with silicon fins and a metal gate with a nitride-cap perpendicular to and over the fins, with source/drain regions, each with an oxide-cap, on the fins on opposite sides of the gate; forming parallel dielectric lines, separated from each other, perpendicular to and over the gate; forming a photoresist over the parallel dielectric lines, forming an opening in the photoresist exposing a nitride-cap between two fins; removing the exposed nitride-cap exposing an underlying metal gate; removing the exposed metal gate and a remainder of the photoresist; forming low-k dielectric lines between the parallel dielectric lines; removing sections of the parallel dielectric lines; forming perpendicular interconnects between the low-k dielectric lines; removing a remainder of the parallel dielectric lines forming trenches; and filling the trenches with metal.

Abstract translation: 公开了用于形成非常接近栅极接触的自对准栅极切割和所得到的器件的方法。 实施例包括：提供具有硅散热片的衬底和金属栅极，其中氮化物帽垂直于翅片和鳍上，源极/漏极区域各自具有氧化物盖，位于栅极的相对侧上的鳍片上; 形成彼此分离的平行介质线，垂直于栅极和栅极上方; 在所述平行介质线上形成光致抗蚀剂，在所述光致抗蚀剂中形成在两个翅片之间暴露氮化物盖的开口; 去除暴露的氮化物盖，暴露下面的金属栅极; 去除暴露的金属栅极和其余的光致抗蚀剂; 在平行介质线之间形成低k介质线; 去除平行介电线路的部分; 在低k介质线之间形成垂直互连; 去除形成沟槽的平行介质线的剩余部分; 并用金属填充沟槽。

公开(公告)号：US20160163584A1

公开(公告)日：2016-06-09

申请号：US14674792

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jia Zeng ,  Youngtag Woo ,  Jongwook Kye

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/027 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.

Abstract translation: 一种方法包括在硬掩模层之上形成心轴元件，在心轴元件上形成第一和第二间隔物，去除心轴元件，限定在第一和第二间隔物之间​​的第一开口，并暴露硬掩模层的一部分并具有 沿第一方向延伸的纵轴，形成覆盖所述第一开口的中间部分的阻挡掩模，所述阻挡掩模具有在与所述第一方向不同的第二方向上延伸的纵向轴线;在所述阻挡掩模的存在下， 阻挡掩模和所述第一和第二间隔物，以限定在所述硬掩模层中沿所述第一方向延伸的对准的第一和第二线段开口，基于所述第一和第二线段开口蚀刻设置在所述硬掩模层下方的电介质层中的凹陷， 并用导电材料填充凹部。