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    CMOS DEVICES AND MANUFACTURING METHOD THEREOF
    11.
    发明申请
    CMOS DEVICES AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190051565A1

    公开(公告)日：2019-02-14

    申请号：US15673519

    申请日：2017-08-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Baars ,  Hans-Juergen Thees ,  Thorsten Kammler

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234

    Abstract: A method of manufacturing a complementary metal-oxide-semiconductor (CMOS) device comprising an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region is provided, that comprises: depositing a raised source and drain (RSD) layer of a first type in the NMOS region and the PMOS region at the same time; selectively removing the RSD layer of the first type in one of the NMOS region and the PMOS region; and depositing an RSD layer of a second type in the one of the NMOS region and the PMOS region.

    Method of forming a semiconductor device structure and semiconductor device structure
    12.
    发明授权
    Method of forming a semiconductor device structure and semiconductor device structure 有权

    公开(公告)号：US09953876B1

    公开(公告)日：2018-04-24

    申请号：US15282211

    申请日：2016-09-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Hans-Juergen Thees

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/51

    CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0883 ,  H01L29/786

    Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

    Reticles for use in forming implant masking layers and methods of forming implant masking layers
    13.
    发明授权
    Reticles for use in forming implant masking layers and methods of forming implant masking layers 有权
    用于形成植入物掩模层的网状物和形成植入物掩蔽层的方法

    公开(公告)号：US09372392B2

    公开(公告)日：2016-06-21

    申请号：US14325515

    申请日：2014-07-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Martin Mazur ,  Dietmar Henke ,  Hans-Juergen Thees

    IPC: G03F1/22 ,  G03F1/24 ,  G03F7/20 ,  G03F1/00

    CPC classification number: G03F1/24 ,  G03F1/22 ,  G03F1/50 ,  G03F7/2026 ,  G03F7/2045

    Abstract: In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.

    Abstract translation: 在一个示例中，本文公开的掩模版包括具有中心的主体，多个曝光图案的布置，其中该布置的中心偏离主体的中心，以及限定在该主体上或之上的至少一个开放特征 标线的主体。 在另一个实例中，公开了一种方法，其包括在多个功能模具上形成光致抗蚀剂层和多个不完全模具，使位于功能模具中的至少一个上的光致抗蚀剂材料和/或至少一个不完全模具 通过掩模版的开放特征执行不完全的裸片曝光处理，以露出位于多个不完全裸片上方的基本上所有的光致抗蚀剂材料，并且显影光致抗蚀剂以去除位于不完全裸片上方的光刻胶材料的部分。

    RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF FORMING IMPLANT MASKING LAYERS
    14.
    发明申请
    RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF FORMING IMPLANT MASKING LAYERS 有权

    公开(公告)号：US20140329173A1

    公开(公告)日：2014-11-06

    申请号：US14325515

    申请日：2014-07-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Martin Mazur ,  Dietmar Henke ,  Hans-Juergen Thees

    IPC: G03F1/22 ,  G03F1/00

    CPC classification number: G03F1/24 ,  G03F1/22 ,  G03F1/50 ,  G03F7/2026 ,  G03F7/2045

    Abstract: In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.

    METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE
    17.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE 有权

    公开(公告)号：US20180096894A1

    公开(公告)日：2018-04-05

    申请号：US15282211

    申请日：2016-09-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Hans-Juergen Thees

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/51

    CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0883 ,  H01L29/786

    Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

    EMBEDDED SIGMA-SHAPED SEMICONDUCTOR ALLOYS FORMED IN TRANSISTORS
    19.
    发明申请
    EMBEDDED SIGMA-SHAPED SEMICONDUCTOR ALLOYS FORMED IN TRANSISTORS 审中-公开
    嵌入式晶体管中形成的SIGMA-形状半导体合金

    公开(公告)号：US20160056261A1

    公开(公告)日：2016-02-25

    申请号：US14466004

    申请日：2014-08-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hans-Juergen Thees ,  Jens-Peter Biethan

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/51 ,  H01L21/311 ,  H01L29/78 ,  H01L21/306 ,  H01L29/423

    CPC classification number: H01L29/6656 ,  H01L21/30608 ,  H01L21/3086 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A method of forming a semiconductor device is disclosed wherein sigma-shaped cavities are formed in alignment with a gate structure such that a cavity tip of the sigma-shaped cavities has a small lateral distance to the channel region, while a lateral distance from the silicon-germanium material filled into the cavity and extending along the sidewall of the gate structure above the active region is at least maintained, if not increased. A semiconductor device is formed wherein the semiconductor device comprises a gate structure disposed over an active region of a semiconductor substrate. The gate structure has a gate electrode and a sidewall spacer structure with a first spacer of L-shape and a second spacer disposed on the first spacer. In alignment with the gate structure, sigma-shaped cavities are formed in the active region and embedded SiGe material is epitaxially grown in the sigma-shaped cavities.

    Abstract translation: 公开了一种形成半导体器件的方法，其中形成与栅极结构对准的σ形空腔，使得σ形空腔的空腔顶端具有与沟道区域的小的横向距离，而与硅的横向距离 如果不增加，填充到空腔中并且沿着活动区域上方的栅极结构的侧壁延伸的锗材料至少被维持。 形成半导体器件，其中半导体器件包括设置在半导体衬底的有源区上的栅极结构。 栅极结构具有栅电极和侧壁间隔结构，其具有L形的第一间隔件和设置在第一间隔件上的第二间隔件。 与栅极结构对准，在活性区域中形成σ形空腔，并且在σ形空腔中外延生长嵌入的SiGe材料。

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