公开(公告)号：US10170617B2

公开(公告)日：2019-01-01

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok Kim ,  Hiroaki Niimi ,  Hoon Kim ,  Puneet Harischandra Suvarna ,  Steven Bentley ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US10170574B2

公开(公告)日：2019-01-01

申请号：US15792206

申请日：2017-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US10141446B2

公开(公告)日：2018-11-27

申请号：US15793545

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Kwan-Yong Lim ,  Steven John Bentley ,  Daniel Chanemougame

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L27/24 ,  H01L29/792 ,  H01L29/78

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20180240875A1

公开(公告)日：2018-08-23

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US09972682B2

公开(公告)日：2018-05-15

申请号：US15004756

申请日：2016-01-22

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US09735111B2

公开(公告)日：2017-08-15

申请号：US14862894

申请日：2015-09-23

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/285 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

公开(公告)号：US09640535B2

公开(公告)日：2017-05-02

申请号：US15175540

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Ruilong Xie

IPC: H01L21/768 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L23/485 ,  H01L21/8238 ,  H01L23/532

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76801 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: A semiconductor device includes an isolation region laterally defining an active region in a semiconductor substrate, a gate structure positioned above the active region, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. An etch stop layer is positioned above and covers a portion of the active region, an interlayer dielectric material is positioned above the active region and covers the etch stop layer, and a confined raised source/drain region is positioned on and in contact with an upper surface of the active region. The confined raised source/drain region extends laterally between and contacts a lower sidewall surface portion of the sidewall spacer and at least a portion of a sidewall surface of the etch stop layer, and a conductive contact element extends through the interlayer dielectric material and directly contacts an upper surface of the confined raised source/drain region.

公开(公告)号：US09589851B2

公开(公告)日：2017-03-07

申请号：US14800970

申请日：2015-07-16

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L23/532 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/535

CPC classification number: H01L21/76832 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0895 ,  H01L29/66795 ,  H01L29/7851

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract translation: 晶体管器件包括衬底; 形成在所述基板上的源极区域和漏极区域; 以及与所述源极区域和所述漏极区域中的至少一个接触形成的源极/漏极接触部，所述源极/漏极接触部包括导电金属和设置在所述导电金属与所述源极和漏极区域中的至少一个之间的双层 包括与导电金属接触的金属氧化物层的双层以及与源区和漏区中的至少一个接触的二氧化硅层。

公开(公告)号：US09412695B1

公开(公告)日：2016-08-09

申请号：US14641699

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hiroaki Niimi ,  Andreas Knorr

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L29/7851 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/66795

Abstract: Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a substrate, and an insulating material over the fin(s) and the substrate; providing barrier structures extending into the insulating material, the barrier structures being disposed along opposing sides of the fin(s); exposing a portion of the fin(s) and the barrier structures; and forming an interconnect structure extending over the fin(s), the barrier structures confining the interconnect structure to a defined dimension transverse to the fin(s). Exposing the portion of the fin(s) and barrier structures may include isotropically etching the insulating material with an etchant that selectively etches the insulating material without affecting a barrier material of the barrier structures.

Abstract translation: 提供了用于电路结构晶体管的方法和互连结构。 所述方法包括例如：在衬底上提供一个或多个鳍片，以及在鳍片和衬底上方的绝缘材料; 提供延伸到所述绝缘材料中的阻挡结构，所述阻挡结构沿着所述鳍片的相对侧布置; 暴露所述鳍片和所述屏障结构的一部分; 以及形成在所述翅片上延伸的互连结构，所述阻挡结构将所述互连结构限制在横向于所述鳍片的限定尺寸。 暴露鳍状物和阻挡结构的部分可以包括用蚀刻剂均匀地蚀刻绝缘材料，该蚀刻剂选择性地蚀刻绝缘材料而不影响阻挡结构的阻挡材料。

公开(公告)号：US11562906B2

公开(公告)日：2023-01-24

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.