公开(公告)号：US09876010B1

公开(公告)日：2018-01-23

申请号：US15342464

申请日：2016-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jagar Singh ,  Jerome Ciavatti

IPC: H01L23/62 ,  H01L27/06 ,  H01L23/522 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L23/5226 ,  H01L23/5228 ,  H01L29/4232 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A resistor is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. The resistor is composed of a material suitable to provide a predetermined resistance to a current to be conducted therethrough. A pair of resistor contacts are electrically connected to the resistor and spaced to provide the predetermined resistance to the current.

公开(公告)号：US09530553B1

公开(公告)日：2016-12-27

申请号：US14929869

申请日：2015-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Singh ,  Jagar Singh ,  Pankaj Marria

IPC: H01F5/00 ,  H01F27/24 ,  H01F17/04 ,  H01F27/28

CPC classification number: H01F19/00 ,  H01F27/255 ,  H01F27/2804 ,  H01F41/046

Abstract: An inductor/transformer device is disclosed including a lower inductor/transformer structure including a first inner core material and a first outer cap layer, an upper inductor/transformer structure positioned above and vertically spaced apart from the lower inductor/transformer structure, the upper inductor/transformer structure including a second inner core material and a second outer cap layer, wherein the lower surface area of the upper inductor/transformer structure is different than the upper surface area of the lower inductor/transformer structure, and an insulating material positioned between the upper surface of the lower inductor/transformer structure and the lower surface of the upper inductor/transformer structure.

Abstract translation: 公开了一种电感器/变压器装置，其包括包括第一内芯材料和第一外盖层的下电感器/变压器结构，位于上部电感器/变压器结构之上并与下部电感器/变压器结构垂直间隔开的上部电感器/变压器结构，上部电感器 /变压器结构，包括第二内芯材料和第二外盖层，其中上电感器/变压器结构的下表面区域不同于下电感器/变压器结构的上表面区域，并且位于 下电感/变压器结构的上表面和上电感/变压器结构的下表面。

公开(公告)号：US20150077086A1

公开(公告)日：2015-03-19

申请号：US14030458

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc

Inventor： Jagar Singh

IPC: H01L29/78 ,  G01B7/02

CPC classification number: H01L29/785 ,  H01L22/14 ,  H01L29/66795

Abstract: A method for accurately electrically measuring a width of a fin of a FinFET, using a semiconductor fin quantum well structure is provided. The semiconductor fin quantum well structure includes a semiconductor substrate and at least one semiconductor fin coupled to the substrate. Each of the semiconductor fin is sandwiched by an electrical isolation layer from a top and a first side and a second side across from the first side, to create a semiconductor fin quantum well. At least one gate material is provided on each side of the electrical isolation layer. A dielectric layer is provided over the top of the electrical isolation layer to further increase the electrical isolation between the gate materials. The width of the semiconductor fin is measured accurately by applying a resonant bias voltage across the fin by applying voltage on the gate materials from either side. The peak tunneling current generated by the applied resonant bias voltage is used to measure width of the fin.

Abstract translation: 提供了使用半导体翅片量子阱结构来精确地电测量FinFET的鳍的宽度的方法。 半导体鳍片量子阱结构包括半导体衬底和耦合到衬底的至少一个半导体鳍片。 半导体翅片的每一个被从第一侧的顶部和第一侧和第二侧的电隔离层夹持，以产生半导体翅片量子阱。 在电绝缘层的每一侧上设置至少一个栅极材料。 在电绝缘层的顶部上方提供介电层，以进一步增加栅极材料之间的电隔离。 通过在两侧的栅极材料上施加电压，通过在鳍片上施加谐振偏压来精确地测量半导体鳍片的宽度。 由施加的谐振偏置电压产生的峰值隧道电流用于测量鳍片的宽度。

公开(公告)号：US20190108942A1

公开(公告)日：2019-04-11

申请号：US15729992

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F41/063 ,  H01F41/12 ,  H01F41/34 ,  H01F5/00 ,  H01F5/06

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

公开(公告)号：US10056368B2

公开(公告)日：2018-08-21

申请号：US15686523

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kasun Anupama Punchihewa ,  Jagar Singh

IPC: H01L27/06 ,  H01L21/265 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/08

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0814 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66136 ,  H01L29/861

Abstract: A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins. The doped region includes a first dopant having a first conductivity type and is contiguous between the adjacent fins. A cathode region is defined by an inner portion of each of the plurality of fins positioned below and contacting the first surface portion and a third portion of the semiconductor substrate positioned below and contacting the second surface portion. The cathode region is contiguous and the dopants in the cathode region and anode region have opposite conductivity types. A junction is defined between the anode region and the cathode region. A first contact interfaces with the anode region.

公开(公告)号：US10020386B1

公开(公告)日：2018-07-10

申请号：US15454511

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Baofu Zhu

IPC: H01L29/735 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L27/0259 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/107

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage, analog bipolar devices and methods of manufacture. The structure includes: a base region formed in a substrate; a collector region formed in the substrate and comprising a deep n-well region and an n-well region; and an emitter region formed in the substrate and comprising a deep n-well region and an n-well region.

公开(公告)号：US09741713B1

公开(公告)日：2017-08-22

申请号：US15138954

申请日：2016-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/66 ,  H01L27/06 ,  H01L29/735 ,  H01L29/73 ,  H01L23/535 ,  H01L29/161 ,  H01L29/36 ,  H01L21/8249 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/26506 ,  H01L21/8249 ,  H01L23/535 ,  H01L27/0623 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/36 ,  H01L29/6625 ,  H01L29/7302 ,  H01L29/735

Abstract: A semiconductor structure includes a semiconductor substrate of n-type or p-type, a well of a type opposite the substrate, the well acting as the base of a diode, a first region of the same type as the substrate at a top of the well, a second region of the same type as the substrate is situated separate from the first region at the top of the well, the first region acting as an emitter of the diode and the second region acting as a collector of the diode, and a gate situated between the first region and second region over a top surface of the well.

公开(公告)号：US09666717B2

公开(公告)日：2017-05-30

申请号：US14217691

申请日：2014-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Konstantin G. Korablev ,  Andy Chih-Hung Wei

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/36 ,  H01L21/265

CPC classification number: H01L29/7851 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).

公开(公告)号：US09543378B2

公开(公告)日：2017-01-10

申请号：US14467420

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/735 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0619 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/735

Abstract: Semiconductor devices and fabrication methods thereof are provided. The semiconductor devices include: a substrate, the substrate including a p-type well adjoining an n-type well; a first p-type region and a first n-type region disposed within the n-type well of the substrate, where the first p-type region at least partially encircles the first n-type region; and a second p-type region and a second n-type region disposed in the p-type well of the substrate, where the second n-type region at least partially encircles the second p-type region. In one embodiment, the first p-type region fully encircles the first n-type region and the second n-type region fully encircles the second p-type region. In another embodiment, the semiconductor device may be a bipolar junction transistor or a rectifier.

Abstract translation: 提供半导体器件及其制造方法。 所述半导体器件包括：衬底，所述衬底包括邻接n型阱的p型阱; 第一p型区域和第一n型区域，其设置在衬底的n型阱内，其中第一p型区域至少部分地环绕第一n型区域; 以及设置在所述基板的p型阱中的第二p型区域和第二n型区域，其中所述第二n型区域至少部分地环绕所述第二p型区域。 在一个实施例中，第一p型区域完全环绕第一n型区域，而第二n型区域完全环绕第二p型区域。 在另一个实施例中，半导体器件可以是双极结型晶体管或整流器。

公开(公告)号：US09418993B2

公开(公告)日：2016-08-16

申请号：US13958938

申请日：2013-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7835

Abstract: Semiconductor devices and methods for manufacturing an LDMOS FinFET integrated circuit. The intermediate semiconductor device includes a substrate, a first well in the substrate, a second well in the substrate, and at least two polysilicon gates. The first well overlaps the second well and the at least one first gate is disposed over the first well and at least one second gate is disposed over the second well. The method includes forming a channel region and a drift region in the substrate, wherein the channel region overlaps the drift region, forming a shallow trench isolation region in the drift region, forming at least one first gate over the channel region, forming at least one second gate over the shallow trench isolation region, and applying at least one metal layer over the at least one first gate and the at least one second gate.

Abstract translation: 用于制造LDMOS FinFET集成电路的半导体器件和方法。 中间半导体器件包括衬底，衬底中的第一阱，衬底中的第二阱以及至少两个多晶硅栅极。 第一阱与第二阱重叠，并且至少一个第一栅极设置在第一阱上，并且至少一个第二栅极设置在第二阱上。 该方法包括在衬底中形成沟道区和漂移区，其中沟道区与漂移区重叠，在漂移区中形成浅沟槽隔离区，在沟道区上形成至少一个第一栅，形成至少一个 在浅沟槽隔离区域上的第二栅极，以及在所述至少一个第一栅极和所述至少一个第二栅极上施加至少一个金属层。