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    Semiconductor structure having test device
    11.
    发明授权
    Semiconductor structure having test device 有权
    具有测试装置的半导体结构

    公开(公告)号：US09500703B2

    公开(公告)日：2016-11-22

    申请号：US14462643

    申请日：2014-08-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Anil Kumar ,  Suresh Uppal ,  Manjunatha Prabhu ,  William McMahon

    IPC: G01R31/26 ,  G01R31/28

    CPC classification number: G01R31/2884 ,  G01R31/2601 ,  G01R31/2644 ,  H01L22/34

    Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

    Abstract translation: 这里提出了包括多个测试装置的半导体结构，所述多个测试装置包括第一测试装置和第二测试装置。 半导体结构还可以包括波形发生电路，波形发生电路被配置为将第一应力信号波形具有第一占空比施加到第一测试装置，第二应力信号波形具有第二占空比到第二测试 设备。 半导体结构可以包括与第一测试装置和第二测试装置中的每一个相关联的选择电路，用于在应力循环和感测周期之间切换。

    INTEGRATED CIRCUIT (IC) DESIGN SYSTEMS AND METHODS USING SINGLE-PIN IMAGINARY DEVICES
    13.
    发明申请
    INTEGRATED CIRCUIT (IC) DESIGN SYSTEMS AND METHODS USING SINGLE-PIN IMAGINARY DEVICES 审中-公开

    公开(公告)号：US20190384885A1

    公开(公告)日：2019-12-19

    申请号：US16008176

    申请日：2018-06-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Heng Lan Lau ,  Manjunatha Prabhu ,  Vikrant Kumar Chauhan ,  Shawn Walsh

    IPC: G06F17/50

    Abstract: In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.

    Planar semiconductor ESD device and method of making same
    15.
    发明授权
    Planar semiconductor ESD device and method of making same 有权
    平面半导体ESD器件及其制造方法

    公开(公告)号：US09343590B2

    公开(公告)日：2016-05-17

    申请号：US14450887

    申请日：2014-08-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar ,  Ruchil Kumar Jain

    IPC: H01L29/861 ,  H01L29/06 ,  H01L27/02 ,  H01L29/66

    CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L29/0684 ,  H01L29/66128

    Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

    Abstract translation: 提供ESD器件用于保护电路免受静电放电，并且包括具有阳极和阴极的平面二极管。 阳极电耦合到电路的信号路径，并且阴极电耦合到电路的地。 ESD装置被配置为在电路的正常操作期间关闭并且响应于信号路径上的静电放电而导通。 器件中的两个耗尽区由隔离阱隔开。 响应于静电放电，耗尽区域调制（例如，加宽和合并），提供用于放电到电路接地的路径。

    Auxiliary gate antenna diodes
    16.
    发明授权
    Auxiliary gate antenna diodes 有权

    公开(公告)号：US10529704B1

    公开(公告)日：2020-01-07

    申请号：US16148323

    申请日：2018-10-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Salvatore Cimino ,  David Pritchard ,  Lixia Lei ,  Heng Yang ,  Manjunatha Prabhu

    IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

    Abstract: One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.

    Methods for an ESD protection circuit including trigger-voltage tunable cascode transistors
    17.
    发明授权
    Methods for an ESD protection circuit including trigger-voltage tunable cascode transistors 有权

    公开(公告)号：US10147715B2

    公开(公告)日：2018-12-04

    申请号：US15481202

    申请日：2017-04-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chien-hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

    IPC: H01L21/8234 ,  H01L27/02 ,  H01L29/74 ,  H01L29/66 ,  H01L29/78

    Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

    Transistors patterned with electrostatic discharge protection and methods of fabrication
    19.
    发明授权
    Transistors patterned with electrostatic discharge protection and methods of fabrication 有权

    公开(公告)号：US10068895B2

    公开(公告)日：2018-09-04

    申请号：US14661202

    申请日：2015-03-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

    IPC: H01L23/62 ,  H01L27/02 ,  H01L29/417

    Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

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