公开(公告)号：US10396084B1

公开(公告)日：2019-08-27

申请号：US15944910

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare ,  Hongsik Yoon

IPC: H01L21/027 ,  H01L27/11 ,  H01L21/033 ,  H01L21/308

Abstract: Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.

公开(公告)号：US10311201B2

公开(公告)日：2019-06-04

申请号：US15670158

申请日：2017-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nigel Chan ,  Germain Bossu

IPC: G06F17/50

Abstract: Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.

公开(公告)号：US10177163B1

公开(公告)日：2019-01-08

申请号：US15895053

申请日：2018-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Elliot John Smith

IPC: H01L23/02 ,  H01L27/11521 ,  H01L29/06 ,  H01L29/10 ,  H01L27/11558 ,  H01L21/762 ,  H01L29/66 ,  H01L29/788 ,  H01L27/12 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/265 ,  H01L21/266

Abstract: One illustrative device disclosed a floating gate capacitor located in and above a first region of an SOI substrate located on a first side of an isolation trench and a transistor device located in and above a second region of the SOI substrate that is on the opposite side of the isolation trench. The device also includes a control gate formed in the bulk semiconductor layer in the first region and a gate structure that extends across the isolation trench and above the first and second regions. A first portion of the gate structure is positioned above the first region and the control gate and a second portion of the gate structure is positioned above the second region, wherein the first portion of the gate structure constitutes a floating gate for the floating gate capacitor and the second portion of the gate structure constitutes a transistor gate structure for the transistor device.

公开(公告)号：US09762245B1

公开(公告)日：2017-09-12

申请号：US15182068

申请日：2016-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael Otto ,  Nigel Chan

IPC: H03K19/00 ,  H03K19/094 ,  H03K19/0948 ,  H03K19/20

CPC classification number: H03K19/09429 ,  H03K19/09487 ,  H03K19/20

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

公开(公告)号：US08921898B1

公开(公告)日：2014-12-30

申请号：US13920780

申请日：2013-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Michael Otto

IPC: H01L27/118 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.

Abstract translation: 一种器件包括多个存储器单元的阵列，至少一个N阱接触区域和至少一个P阱接触区域。 存储单元布置成多行和多列。 每列包括N阱区和至少一个P阱区。 N阱和P阱区域在柱的第一端和柱的第二端之间延伸。 每个N阱接触区域电接触N阱区域中的至少一个，其中至少一个柱的N阱区域仅在柱的第一和第二端中的一个处电接触。 每个P阱接触区域电接触至少一个P阱区域，其中至少一个柱的P阱区域仅在柱的第一和第二端中的一个处电接触。

公开(公告)号：US20200343248A1

公开(公告)日：2020-10-29

申请号：US16396916

申请日：2019-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Germain Bossu ,  Nigel Chan

IPC: H01L27/11 ,  H01L29/08 ,  H01L27/02

Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

公开(公告)号：US10559490B1

公开(公告)日：2020-02-11

申请号：US16107563

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Ming-Cheng Chang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/306

Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.

公开(公告)号：US10418380B2

公开(公告)日：2019-09-17

申请号：US15664061

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/266

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.

公开(公告)号：US20190172832A1

公开(公告)日：2019-06-06

申请号：US15830671

申请日：2017-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Ralf Van Bentum

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L27/02

Abstract: A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.

公开(公告)号：US20170345914A1

公开(公告)日：2017-11-30

申请号：US15648889

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/308 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.