公开(公告)号：US20200035786A1

公开(公告)日：2020-01-30

申请号：US16044544

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Nigel G. Cave ,  Steven R. Soss ,  Daniel Chanemougame ,  Steven Bentley ,  Rohit Galatage ,  Bum Ki Moon

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/08

Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

公开(公告)号：US10381459B2

公开(公告)日：2019-08-13

申请号：US15865973

申请日：2018-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Yi Qi ,  Nigel G. Cave ,  Edward J. Nowak ,  Andreas Knorr

IPC: H01L21/44 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/308 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

公开(公告)号：US09978608B2

公开(公告)日：2018-05-22

申请号：US15271511

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Nigel G. Cave ,  Lars Liebmann

IPC: H01L21/70 ,  H01L21/308 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for fabricating fins for a fin-type field-effect transistor (FinFET) and fin structures for a FinFET. A conformal layer is formed that includes respective first portions on sidewalls of first hardmask sections previously formed on a substrate, a recess between the first portions on the sidewalls of each adjacent pair of the first hardmask sections, and a second portion between the substrate and the recess. The conformal layer is constituted by a second material chosen to etch selectively to the first material constituting the first hardmask sections. A spacer is formed in each recess and masks the respective second portion of the conformal layer. The conformal layer is then etched to form second hardmask sections each comprised of one of the second portions of the conformal layer. The substrate is etched with the first and second hardmask sections masking the substrate to form a plurality of fins.

公开(公告)号：US09947589B1

公开(公告)日：2018-04-17

申请号：US15600874

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Lars W. Liebmann ,  Andre P. Labonte ,  Nigel G. Cave ,  Mark V. Raymond

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L21/823437 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76892 ,  H01L21/76895 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L23/535 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/785

Abstract: A transistor is formed above an active region. The transistor includes a gate structure, a first gate cap layer and a first sidewall spacer positioned adjacent sidewalls of the gate structure. Source/drain contacts are formed adjacent the first sidewall spacer. The first gate cap layer and a portion of the first sidewall spacer are removed to define a gate contact cavity that exposes a portion of the gate structure and an upper portion of the SD contacts. A second spacer and a conductive gate plug are formed in the gate contact cavity. Upper portions of the SD contacts positioned adjacent the second spacer are removed to define a gate cap cavity. A second gate cap layer is formed in the gate cap cavity. An insulating layer is formed above the second gate cap layer. A first conductive structure is formed in the insulating layer conductively coupled to the gate structure.