公开(公告)号：US20100009503A1

公开(公告)日：2010-01-14

申请号：US12170321

申请日：2008-07-09

申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

公开(公告)号：US20130105881A1

公开(公告)日：2013-05-02

申请号：US13646500

申请日：2012-10-05

申请人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

发明人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

IPC分类号： H01L29/788 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/66825

摘要： A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.

摘要翻译： 非易失性存储器制造工艺包括在形成隔离区之前形成完整的存储单元层堆叠。 存储单元层堆叠包括附加位置保持控制栅层。 在形成层堆叠列之后，附加的控制栅层将被并入在覆盖的控制栅极层和下面的中间介质层之间。 附加控制栅极层与柱之间的隔离区域自对准，同时将覆盖的控制栅极层蚀刻成用于与附加控制栅极层接触的线。 在一个实施例中，占位符控制栅极层有助于与上覆控制栅极层的接触点，使得选择栅极形成不需要控制栅极层与电荷存储层之间的接触。

公开(公告)号：US07915124B2

公开(公告)日：2011-03-29

申请号：US12170321

申请日：2008-07-09

申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

公开(公告)号：US20100006915A1

公开(公告)日：2010-01-14

申请号：US12170327

申请日：2008-07-09

申请人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

发明人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/1203

摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 给定的存储单元在浮动栅极上方具有电介质盖。 在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。 电介质盖减少了浮动栅极和控制栅极之间的漏电流。 电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

公开(公告)号：US08492224B2

公开(公告)日：2013-07-23

申请号：US13163538

申请日：2011-06-17

申请人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

摘要翻译： 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

公开(公告)号：US20110309426A1

公开(公告)日：2011-12-22

申请号：US13163538

申请日：2011-06-17

申请人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

摘要翻译： 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

公开(公告)号：US06514860B1

公开(公告)日：2003-02-04

申请号：US09892750

申请日：2001-06-28

申请人： Lynne A. Okada ,  Fei Wang ,  James K. Kai

发明人： Lynne A. Okada ,  Fei Wang ,  James K. Kai

IPC分类号： H01L2144

CPC分类号： H01L21/76808

摘要： A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.

摘要翻译： 制造半导体器件的方法包括：在第一层上形成第二阻挡层，在第二阻挡层上形成第一介电层，在第一介电层上形成第二电介质层，蚀刻第一和第二电介质层，形成第 通过第一电介质层和第二电介质层开口，在蚀刻第二介电层之前将有机填充材料沉积在开口中并去除一部分有机填充材料以形成沟槽。 然后可以完全去除有机填充材料，并且蚀刻第二阻挡层以暴露第一层。 然后用导电材料填充沟槽和通孔以形成特征。

公开(公告)号：US06221740B1

公开(公告)日：2001-04-24

申请号：US09371436

申请日：1999-08-10

申请人： Michael A. Bryan ,  James K. Kai

发明人： Michael A. Bryan ,  James K. Kai

IPC分类号： H01L2130

CPC分类号： B32B43/006 ,  B28D5/0011 ,  B28D5/0023 ,  B28D5/0064 ,  B28D5/0082 ,  H01L21/67092 ,  Y10T29/53683 ,  Y10T156/1939 ,  Y10T225/12 ,  Y10T225/18 ,  Y10T225/30 ,  Y10T225/386

摘要： A cleaving tool provides pressurized gas to the edge of a substrate to cleave the substrate at a selected interface. A substrate, such as a bonded substrate, is loaded into the cleaving tool, and two halves of the tool are brought together to apply a selected pressure to the substrate. A compliant pad of selected elastic resistance provides support to the substrate while allowing the substrate to expand during the cleaving process. Bringing the two halves of the tool together also compresses an edge seal against the perimeter of the substrate. A thin tube connected to a high-pressure gas source extends through the edge seal and provides a burst of gas to separate the substrate into at least two sheets. In a further embodiment, the perimeter of the substrate is struck with an edge prior to applying the gas pressure.

摘要翻译： 切割工具将加压气体提供到衬底的边缘以在所选择的界面处切割衬底。 衬底（例如键合衬底）被装载到劈开工具中，并且工具的两半被聚集在一起以将选择的压力施加到衬底上。 所选择的弹性阻力的柔性衬垫提供对衬底的支撑，同时允许衬底在裂开过程期间膨胀。 将工具的两个一半带到一起也可压缩衬底周边的边缘密封。 连接到高压气体源的细管延伸穿过边缘密封件并且提供气泡，以将基底分离成至少两个片。 在另一个实施例中，在施加气体压力之前，衬底的周边被边缘撞击。

公开(公告)号：US5841196A

公开(公告)日：1998-11-24

申请号：US970314

申请日：1997-11-14

申请人： Subhash Gupta ,  Robert Flores ,  Michael Ross Stamm ,  Eric Thomas Sharp ,  Erich W. E. Denninger ,  Pamela G. Dye ,  Joel Samuel Utz ,  James K. Kai

发明人： Subhash Gupta ,  Robert Flores ,  Michael Ross Stamm ,  Eric Thomas Sharp ,  Erich W. E. Denninger ,  Pamela G. Dye ,  Joel Samuel Utz ,  James K. Kai

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/00

CPC分类号： H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via exterds a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via. The second stage includes a second sidewall stage extending from the first sidewall stage at a second angle between 40.degree. and 70.degree.. A third etch step is then performed to further remove portions of the dielectric layer to form a third and final. stage of the fluted via. The fluted via extends from an upper surface of the dielectric layer to an upper surface of the first conductive layer. The third stage includes a third stage sidewall extending from said second stage side wall to said upper surface of said first conductive layer at an angle between 60.degree. and 80.degree..

摘要翻译： 一种在半导体器件的层间电介质中形成通孔的方法，其中通孔具有带槽纹的侧壁。 提供具有形成在其上的第一导电层的半导体衬底。 然后在第一导电层上形成电介质层。 在介电层上沉积光致抗蚀剂层，并且在光致抗蚀剂层中形成接触开口以暴露电介质层的接触区域。 执行第一蚀刻步骤以去除接近接触区域的电介质层的部分，以形成槽纹通孔的第一级。 第一级包括从电介质层的上表面以小于50°的角度延伸的第一侧壁级。 槽纹通过的第一阶段通过大于接触开口的横向尺寸的第一横向距离。 然后执行第二蚀刻步骤以进一步去除介电层的部分以形成槽纹通孔的第二级。 第二阶段包括从第一侧壁台以40°至70°之间的第二角度延伸的第二侧壁台。 然后执行第三蚀刻步骤以进一步去除介电层的部分以形成第三和最终。 槽的通道的阶段。 带槽通孔从电介质层的上表面延伸到第一导电层的上表面。 第三级包括第三级侧壁，从第二级侧壁延伸至所述第一导电层的上表面，角度为60°至80°。

公开(公告)号：US06670265B2

公开(公告)日：2003-12-30

申请号：US09326744

申请日：1999-06-04

申请人： Fei Wang ,  James K. Kai ,  Angela T. Hui

发明人： Fei Wang ,  James K. Kai ,  Angela T. Hui

IPC分类号： H01L214763

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/76804

摘要： An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch gases to eliminate mid via etch stop and to maintain selectivity over underlying etch-stop layers.

摘要翻译： 用于在高密度等离子体蚀刻反应器中蚀刻低K自旋电介质如HSQ的集成电路晶片和制造工艺利用屋顶和壁温度来改善晶片间的均匀性，并且将C4F8和C2F6的气体混合物蚀刻到 通过蚀刻停止消除中间，并保持对底层蚀刻停止层的选择性。