公开(公告)号：US20170292986A1

公开(公告)日：2017-10-12

申请号：US15625609

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/12 ,  G01R31/26 ,  G01R31/28

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US09702926B2

公开(公告)日：2017-07-11

申请号：US14288278

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/26 ,  G01R31/12

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US09460806B2

公开(公告)日：2016-10-04

申请号：US14680228

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Akhilesh Gautam ,  Suresh Uppal

IPC: H01L27/112 ,  H01L21/66 ,  G11C17/12 ,  G01R31/26

CPC classification number: G11C17/12 ,  G01R31/26 ,  H01L22/34 ,  H01L27/11206 ,  H01L29/205

Abstract: A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.

Abstract translation: 提供了一种形成能够存储两倍于常规OTPROM的位数的OTPROM的方法，而不增加设备的总体大小。 实施例包括形成OTPROM，OTPROM阵列具有多个形成的器件; 接收二进制代码来编程OTPROM阵列; 将二进制代码分离成第一部分和第二部分; 通过以下方式对每个器件进行编程：通过以下方式对每个器件进行编程：将每个器件的栅极氧化层形成为与二进制代码的第一部分对应的厚度，并且选择性地将TDDB应力施加到对应于第二部分的栅极氧化物层 二进制代码; 用多位读出放大器检测每个器件放电的Idsat电平; 并且基于检测到的Idsat级别读取每个设备的状态。

公开(公告)号：US09372226B2

公开(公告)日：2016-06-21

申请号：US14337290

申请日：2014-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh Uppal ,  Randy W. Mann ,  William McMahon

IPC: G06F17/00 ,  G01R31/28 ,  H01L23/525 ,  H01L21/66

CPC classification number: G01R31/2884 ,  G01R31/2644 ,  H01L22/14 ,  H01L22/34 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

Abstract translation: 描述了晶片测试结构和提供晶片测试结构的方法。 这些方法包括：在晶片上制造多个测试装置和多个保险丝装置，每个测试装置具有与其相关联的相应的熔丝装置，其在测试装置故障时断开电路; 以及制造选择电路，其操作以选择性地将一个测试装置连接到感测触点焊盘，并且将其它测试装置连接到应力接触焊盘。 选择电路通过与感测接触焊盘的电接触便于感测一个测试装置的一个或多个电信号，同时通过与应力接触焊盘电接触来测试其它测试装置。 在一个实施例中，每个测试装置具有相应的第一和第二开关装置，其可操作以选择性地将测试装置电连接到感测或应力接触垫。 在另一个实施例中，该方法包括使用测试结构的晶片测试。

公开(公告)号：US10147496B2

公开(公告)日：2018-12-04

申请号：US15881356

申请日：2018-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  G11C17/18 ,  H01L27/112

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US10106892B1

公开(公告)日：2018-10-23

申请号：US15692816

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shahab Siddiqui ,  Abu Naser Zainuddin ,  Beth Baumert ,  Suresh Uppal

IPC: H01L21/02 ,  H01L21/306 ,  C23C16/455 ,  C01B33/149 ,  C01B21/06 ,  C01F7/02 ,  C01F17/00

Abstract: Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.

公开(公告)号：US10054630B2

公开(公告)日：2018-08-21

申请号：US15625609

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/26 ,  G01R31/12 ,  G01R31/28

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US09599656B2

公开(公告)日：2017-03-21

申请号：US14553863

申请日：2014-11-25

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon ,  Eduard A. Cartier

IPC: G01R31/00 ,  G01R31/14 ,  G01R31/28

CPC classification number: G01R31/14 ,  G01R31/2879

Abstract: At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.

公开(公告)号：US20160204098A1

公开(公告)日：2016-07-14

申请号：US15080090

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L27/02 ,  H01L21/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

公开(公告)号：US20160104541A1

公开(公告)日：2016-04-14

申请号：US14514289

申请日：2014-10-14

Applicant: GlobalFoundries Inc.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract translation: 所公开的至少一种方法，装置和系统涉及将数据硬编码到集成电路装置中。 提供集成电路装置。 接收到集成电路装置的一部分的硬布线信息的数据。 应力电压信号被提供给集成电路器件的晶体管的一部分，用于引起晶体管部分的电介质击穿以硬接线数据。