公开(公告)号：US20170250191A1

公开(公告)日：2017-08-31

申请号：US15053485

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/308 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/12 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/1207 ,  H01L28/00 ,  H01L29/42336 ,  H01L29/42352

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US20150145061A1

公开(公告)日：2015-05-28

申请号：US14590076

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

Abstract translation: 器件包括位于半导体衬底中的第一和第二间隔开的有源区，位于第一和第二间隔开的有源区之间的隔离区和位于第一有源区上的栅极绝缘材料层。 第一导线特征从第一有源区连续延伸并跨越隔离区到第二有源区，其中第一导线特征包括位于第一有源区上的栅极绝缘材料层正上方的第一部分， 以及与第二有源区域导电接触的第二部分。

公开(公告)号：US08956928B2

公开(公告)日：2015-02-17

申请号：US13689979

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L21/00 ,  H01L21/60 ,  H01L29/66 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region.

Abstract translation: 一个器件包括形成在半导体衬底中的第一和第二间隔开的有源区，位于第一有源区上的栅极绝缘材料层，和具有位于栅绝缘材料上方的第一部分的导线特征，以及第二部分 导电地接触第二活性区域。 一种方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区上的栅极绝缘材料的一部分 区域以暴露第二有源区域的一部分，以及形成导线特征，其包括位于形成在第一有源区上的栅绝缘材料层之上的第一部分和与第二有源区的暴露部分导电接触的第二部分 地区。

公开(公告)号：US08951920B2

公开(公告)日：2015-02-10

申请号：US14446797

申请日：2014-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L21/31 ,  H01L23/495

CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad.

Abstract translation: 形成导电接触着陆焊盘和晶体管的方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，并执行蚀刻工艺以去除 形成在第二有源区上的栅极绝缘材料层，从而露出第二有源区。 该方法还包括执行公共处理操作，以在晶体管的第一有源区上形成栅极绝缘材料层上方的栅电极结构，以及与第二有源区导电耦合的导电接触着陆焊盘，并形成接触 到导电接触着陆垫。

公开(公告)号：US20140203339A1

公开(公告)日：2014-07-24

申请号：US14226176

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.

Abstract translation: 半导体器件包括位于有源区上方的高k金属栅电极结构，具有位于栅极高度的顶表面，并且包括高k电介质材料和电极金属。 引出的漏极和源极区域横向邻近高k金属栅极电极结构定位并连接到有源区域，并且每个升高的漏极和源极区域的顶表面位于栅极下方的接触高度水平处 身高。 蚀刻停止层位于凸起的漏极和源极区域的顶表面上方，并且接触元件连接到凸起的漏极和源极区域之一，接触元件延伸穿过蚀刻停止层， k金属栅极电极结构和升高的漏极和源极区域。

公开(公告)号：US10535674B2

公开(公告)日：2020-01-14

申请号：US15653661

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11568 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11582 ,  H01L49/02

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US09929148B1

公开(公告)日：2018-03-27

申请号：US15439444

申请日：2017-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Frank Jakubowski

IPC: H01L23/52 ,  H01L27/06 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L23/31 ,  H01L29/49 ,  H01L49/02 ,  H01L21/762 ,  H01L21/84 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L27/0629 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/3178 ,  H01L23/535 ,  H01L27/108 ,  H01L27/1203 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/495

Abstract: The present disclosure provides semiconductor devices and manufacturing techniques in which a buried capacitive structure may be provided at the level of the buried insulating layer of an SOI device, thereby providing reduced process complexity compared to conventional strategies, while still preserving superior routing capabilities above the buried capacitive structures.

公开(公告)号：US08962414B1

公开(公告)日：2015-02-24

申请号：US13954530

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823425 ,  H01L21/823468 ,  H01L29/6656

Abstract: In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures. After performing an implantation sequence into the sidewall spacers using adjacent gate structures as implantations masks, shadowing lower portions of the sidewall spacers, an etching process is performed for removing implanted portions from the sidewall spacers, leaving lower shadowed portions of the sidewall spacer as shaped sidewall spacers.

Abstract translation: 在本公开的方面，在制造期间的非常早的阶段提供了栅极电介质的可靠封装。 在其他方面，提供了一种半导体器件，其中保持了栅极电介质材料的可靠封装，可靠的封装存在于制造期间的早期阶段。 在实施例中，在半导体衬底的表面上设置具有多个栅极结构的半导体器件。 侧壁间隔件形成在表面上并且与多个栅极结构中的每一个相邻，其中侧壁间隔物覆盖多个栅极结构中的每一个的侧壁表面。 在使用相邻栅极结构作为注入掩模的侧壁间隔件中进行植入序列之后，遮蔽侧壁间隔物的下部，执行蚀刻工艺以从侧壁间隔物去除植入部分，从而使侧壁间隔件的较低阴影部分成为成形侧壁 间隔物

公开(公告)号：US20140335668A1

公开(公告)日：2014-11-13

申请号：US14446797

申请日：2014-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L23/00 ,  H01L29/66

CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad.

Abstract translation: 形成导电接触着陆焊盘和晶体管的方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，并执行蚀刻工艺以去除 形成在第二有源区上的栅极绝缘材料层，从而露出第二有源区。 该方法还包括执行公共处理操作，以在晶体管的第一有源区上形成栅极绝缘材料层上方的栅电极结构，以及与第二有源区导电耦合的导电接触着陆焊盘，并形成接触 到导电接触着陆垫。

公开(公告)号：US08823149B2

公开(公告)日：2014-09-02

申请号：US13710575

申请日：2012-12-11

Applicant: GlobalFoundries Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L23/495 ,  H01L21/31

CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

Abstract: One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same conductive material as the gate electrode, and a contact that is coupled to the contact landing pad. One method herein includes forming first and second spaced-apart active regions, forming a layer of gate insulation material on the active regions, performing an etching process to remove the gate insulation material formed on the second active region, performing a common process operation to form a gate electrode structure above the gate insulation material on the first active region and the contact landing pad that is conductively coupled to the second active region and forming a contact to the contact landing pad.

Abstract translation: 本文中的一个器件包括第一和第二间隔开的有源区，形成在第一有源区中和之上的晶体管，其中晶体管具有栅电极，耦合到第二有源区的导电接触着陆焊盘，其中接触着地 焊盘由与栅极电极相同的导电材料制成，以及耦合到触点着陆焊盘的触点。 这里的一种方法包括形成第一和第二间隔开的有源区域，在有源区域上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区域上的栅极绝缘材料，执行共同的工艺操作以形成 位于第一有源区上的栅极绝缘材料上方的栅极电极结构和与第二有源区导电耦合并形成与接触着陆焊盘接触的触点接合焊盘。