公开(公告)号：US20210057462A1

公开(公告)日：2021-02-25

申请号：US16544074

申请日：2019-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L27/144 ,  H01L29/04 ,  H01L29/165 ,  H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/105 ,  H01L31/18

Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.

公开(公告)号：US10910308B2

公开(公告)日：2021-02-02

申请号：US15975041

申请日：2018-05-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/768 ,  H01L23/00 ,  H01L23/62

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

公开(公告)号：US10833072B1

公开(公告)日：2020-11-10

申请号：US16404161

申请日：2019-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Mark Levy ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L27/082 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8222 ,  H01L21/225 ,  H01L21/311 ,  H01L27/06 ,  H01L21/762 ,  H01L23/544

Abstract: Structures for a heterojunction bipolar transistor and methods of fabricating such structures. A hardmask is formed that includes an opening over a first portion of a substrate in a first device region and a shape over a second portion of the substrate in a second device region. An oxidized region in the first portion of the substrate while the shape blocks oxidation of the second portion of the substrate. The oxidized region is subsequently removed from the first portion of the substrate to define a recess. A first base and a first emitter of a first heterojunction bipolar transistor are formed over the first portion of the substrate in the first device region, and a second base and a second emitter of a second heterojunction bipolar transistor are formed in the recess over the second portion of the substrate in the second device region.

公开(公告)号：US20190273132A1

公开(公告)日：2019-09-05

申请号：US15911831

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L29/06 ,  H01L23/48 ,  H01L21/764 ,  H01L21/762 ,  H01L21/768

Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

公开(公告)号：US10388728B1

公开(公告)日：2019-08-20

申请号：US15911831

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L29/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764

Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

公开(公告)号：US10331844B2

公开(公告)日：2019-06-25

申请号：US15290569

申请日：2016-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  James W. Adkisson

IPC: G06F17/50 ,  H01L27/082 ,  H01L21/8222 ,  H01L21/027

Abstract: Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which differs from the first BEOL stack, is determined such that, when the second BEOL stack is coupled with the emitter of the bipolar junction transistor, the first current ratio is changed to a second current ratio. The change from the first current ratio to the second current ratio, which is based on the change from the first layout for the first BEOL stack to the second layout for the second BEOL stack, is accomplished without changing a front-end-of-line (FEOL) layout of the bipolar junction transistor.

公开(公告)号：US10217852B1

公开(公告)日：2019-02-26

申请号：US15948486

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  James R. Elliott

IPC: H01L23/552 ,  H01L29/737 ,  H01L29/10 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. A trench isolation region surrounds an active region that includes a collector, and a base layer includes a first section composed of a single-crystal semiconductor material that is arranged over the active region and a second section composed of polycrystalline semiconductor material that is arranged over the trench isolation region. A first semiconductor layer of the second section of the base layer is removed selective to a second semiconductor layer of the second section of the base layer to define a gap arranged in a vertical direction between the second semiconductor layer of the second section of the base layer and the trench isolation region. An emitter is formed on the first section of the base layer.

公开(公告)号：US10197730B1

公开(公告)日：2019-02-05

申请号：US15806931

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yves T. Ngu ,  Vibhor Jain ,  John J. Ellis-Monaghan ,  Sebastian Theodore Ventrone ,  Saurabh Sirohi

IPC: G02B6/12 ,  G02B6/293 ,  G02F1/01 ,  G02F1/025

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical via connections in chip-to-chip transmission in a 3D chip stack structure using an optical via, and methods of manufacture. The structure has a first wafer, including a first waveguide coupled to an optical resonator in the first wafer, and a second wafer, including a second waveguide, located over the first wafer. The structure also includes an optical via extending between the optical resonator of the first wafer and the second waveguide of the second wafer to optically couple the first and second waveguides.

公开(公告)号：US10134880B2

公开(公告)日：2018-11-20

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US20180102289A1

公开(公告)日：2018-04-12

申请号：US15290569

申请日：2016-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  James W. Adkisson

IPC: H01L21/8222 ,  H01L27/082 ,  G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0274 ,  H01L21/8222 ,  H01L27/082 ,  H01L27/0823

Abstract: Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which differs from the first BEOL stack, is determined such that, when the second BEOL stack is coupled with the emitter of the bipolar junction transistor, the first current ratio is changed to a second current ratio. The change from the first current ratio to the second current ratio, which is based on the change from the first layout for the first BEOL stack to the second layout for the second BEOL stack, is accomplished without changing a front-end-of-line (FEOL) layout of the bipolar junction transistor.