公开(公告)号：US20100306568A1

公开(公告)日：2010-12-02

申请号：US12857049

申请日：2010-08-16

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: G06F1/04

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US20100046601A1

公开(公告)日：2010-02-25

申请号：US12606751

申请日：2009-10-27

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03K5/159

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract translation: 公开了各种示例性实施例。 根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。 适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

公开(公告)号：US07623600B2

公开(公告)日：2009-11-24

申请号：US10880959

申请日：2004-06-30

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H04L27/08

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract translation: 在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。 自动增益控制级可以包括具有可调节带宽的连续时间滤波器。 阈值调整信号可以应用于自动增益控制级的输出。 均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。

公开(公告)号：US07511582B2

公开(公告)日：2009-03-31

申请号：US10623992

申请日：2003-07-21

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03L7/00

CPC classification number: H03L7/099 ,  H04J3/0688

Abstract: The present invention provides a clock circuit to produce a Reference Clock Signal used to latch data between first bit stream(s) and second bit stream(s), wherein the number and bit rate of the first bit stream(s) and the second bit stream(s) differ. The VCO generates one of a number of inputs to a PLL within the clock circuit. At a minimum, these inputs include a first bit stream data clock. Additionally, these inputs may further include a Loop Timing Clock Signal, an External Reference Clock Signal, and/or a Reverse Clock Signal for the PLL. The input provided by the VCO make up a VCO Output Signal wherein a filtering circuit that circuit includes a capacitor and a resistor reduces noise contained within the VCO Output Signal.

Abstract translation: 本发明提供了一种时钟电路，用于产生用于在第一比特流和第二比特流之间锁存数据的参考时钟信号，其中第一比特流和第二比特流的数量和比特率 流不同。 VCO产生时钟电路内的PLL的多个输入之一。 至少这些输入包括第一位流数据时钟。 此外，这些输入还可以包括用于PLL的环路定时时钟信号，外部参考时钟信号和/或反向时钟信号。 由VCO提供的输入构成VCO输出信号，其中包括电容器和电阻的电路的滤波电路减少了VCO输出信号中包含的噪声。

公开(公告)号：US20070069817A1

公开(公告)日：2007-03-29

申请号：US11559195

申请日：2006-11-13

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03G3/10

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20050271169A1

公开(公告)日：2005-12-08

申请号：US10880959

申请日：2004-06-30

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03G3/30 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L27/08

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract translation: 在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。 自动增益控制级可以包括具有可调节带宽的连续时间滤波器。 阈值调整信号可以应用于自动增益控制级的输出。 均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。

公开(公告)号：US20050156653A1

公开(公告)日：2005-07-21

申请号：US11078151

申请日：2005-03-11

Applicant: Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

Inventor： Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC: H03K19/0185 ,  H04L7/00 ,  H03L5/00

CPC classification number: H03K19/018585 ,  H04L7/0008

Abstract: An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

Abstract translation: 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。

公开(公告)号：US06690949B1

公开(公告)日：2004-02-10

申请号：US09410136

申请日：1999-09-30

Applicant: Danny Shamlou ,  Guangming Yin ,  Ricke Waylan Clark ,  Paul A. Underbrink

Inventor： Danny Shamlou ,  Guangming Yin ,  Ricke Waylan Clark ,  Paul A. Underbrink

IPC: H04B138

CPC classification number: H04B1/406

Abstract: A communication system for the wireless transmission of information through a single antenna is disclosed. The communication system comprises a handset and one or more modules capable of being coupled to the handset. The handset processes baseband information signals being received and transmitted, and transmits and receives radio frequency (RF) information signals through its antenna. Each module is removably couplable to the handset for converting baseband information signals into RF information signals for transmission, and for converting received RF information signals into baseband information signals. Each removably couplable module is optimized to enable wireless communication in accordance with at least one communication standard when coupled to the handset. By coupling the appropriate module with the handset, wireless communication in a number of geographic locations may be achieved.

Abstract translation: 公开了一种用于通过单个天线无线传输信息的通信系统。 通信系统包括手机和能够耦合到手机的一个或多个模块。 手机处理接收和发送的基带信息信号，并通过其天线发送和接收射频（RF）信息信号。 每个模块可拆卸地耦合到手机，用于将基带信息信号转换成用于传输的RF信息信号，并将接收的RF信息信号转换为基带信息信号。 每个可移除耦合的模块被优化以在耦合到手机时根据至少一个通信标准实现无线通信。 通过将适当的模块与手机耦合，可以实现多个地理位置的无线通信。

公开(公告)号：US09401594B2

公开(公告)日：2016-07-26

申请号：US14374498

申请日：2012-02-15

Applicant: Quanqing Zhu ,  Guangming Yin

Inventor： Quanqing Zhu ,  Guangming Yin

IPC: H02H9/00 ,  H02H3/22 ,  H04L25/02

CPC classification number: H02H3/22 ,  H04L25/0272 ,  H04L25/028

Abstract: An integrated circuit device (200) includes a first and second differential I/O pins (TRXP/TRXN) and a surge protection circuit. The surge protection circuit includes a protection transistor, a positive surge detection circuit, and a negative surge detection circuit. The protection transistor is connected between the first and second I/O pins and has a gate to receive a control signal (CTRL). The protection transistor is turned on to connect the I/O pins together if the positive surge detection circuit detects a positive surge energy on either of the I/O pins and/or if the negative surge detection circuit detects a negative surge energy on either of the I/O pins. The surge protection circuit provides increased protection for Ethernet device against undesirable energy in a manner that does not adversely affect the performance of the device.

Abstract translation: 集成电路装置（200）包括第一和第二差分I / O引脚（TRXP / TRXN）和浪涌保护电路。 浪涌保护电路包括保护晶体管，正浪涌检测电路和负浪涌检测电路。 保护晶体管连接在第一和第二I / O引脚之间，并具有接收控制信号（CTRL）的门。 如果正浪涌检测电路检测到任一个I / O引脚上的正浪涌能量和/或如果负浪涌检测电路检测到任何一个的负浪涌能量，则保护晶体管导通以将I / O引脚连接在一起 I / O引脚。 浪涌保护电路以不会对设备性能产生不利影响的方式为以太网设备提供更高的防护性能，防止不需要的能量。

公开(公告)号：US08779859B2

公开(公告)日：2014-07-15

申请号：US13570062

申请日：2012-08-08

Applicant: Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

Inventor： Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

IPC: H03F1/22

CPC classification number: H03F1/223 ,  H03F3/193

Abstract: Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.

Abstract translation: 用于产生多共源共栅放大器偏置电压的技术。 在一方面，提供了一种多共源共栅偏压网络，偏置网络中的每个晶体管是多共源共栅放大器中对应的晶体管的复制品，使多级共源共栅放大器中的晶体管能够精确偏置。 在另一方面，用于多重共源共栅放大器的电压源与用于复制偏压网络的电压源分开提供，以有利地将放大器电压源与偏置网络电压源的变化分离。 在另一方面，多并联放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。 由于放大器的增益取决于共源共栅放大器的偏置电压，所以可以以这种方式调节放大器的增益，而不将可变增益元件直接引入放大器信号路径。