公开(公告)号：US06453381B1

公开(公告)日：2002-09-17

申请号：US09453045

申请日：1999-12-02

Applicant: Der-Min Yuan ,  Gyh-Bin Wang

Inventor： Der-Min Yuan ,  Gyh-Bin Wang

IPC: G06F1200

CPC classification number: G11C7/1066 ,  G11C7/1018 ,  G11C7/1072

Abstract: In this invention a double data rate (DDR) DRAM is read and written with data coherence. The data is in the form of a data burst either interleaved or sequential and of any length. The data is read from the DDR DRAM depending on whether the starting address is even or odd and taking into consideration CAS latency. Both edges of the clock are used to transfer data in and out of the DDR DRAM. To write data only the starting address of the data burst is used to maintain data coherence. Data coherence is assured by a write followed by a read of the same data to and from the same memory cell.

Abstract translation: 在本发明中，用数据一致性读写双数据速率（DDR）DRAM。 数据是数据突发的形式，交织或连续且任意长度。 数据从DDR DRAM读取，取决于起始地址是偶数还是奇数，并考虑到CAS延迟。 时钟的两个边缘用于将数据传入和传出DDR DRAM。 为了写入数据，仅使用数据突发的起始地址来维持数据一致性。 数据一致性是通过写入，然后读取相同的数据到和从同一个存储器单元来确保的。

公开(公告)号：US06198340B1

公开(公告)日：2001-03-06

申请号：US09246421

申请日：1999-02-08

Applicant: Tah-Kang Joseph Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang

Inventor： Tah-Kang Joseph Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang

IPC: G05F110

CPC classification number: H02M3/073

Abstract: In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are connected to a pump circuit output by means of two pass gate circuits. The transistors in each pass gate are controlled such that one pass gate circuit conducts in a first half of a clock cycle and the second pass gate circuit conducts in a second half of a clock period. Each pass gate is driven such that the full boosted signal is transferred to the output of the pump circuit and is not diminished by a threshold voltage of the pass gate circuit. The efficiency of this design keeps the output capacitor charged to a value close to the average value of boosted signal.

Abstract translation: 在本发明中，升压电路由两个互补的升压信号驱动。 两个升压信号产生两个互补的升压信号，它们通过两个通过门电路连接到泵电路输出端。 控制每个通过栅极中的晶体管，使得一个通过栅极电路在时钟周期的前半个时间内导通，并且第二个通过门电路在时钟周期的后半段内导通。 驱动每个通过门，使得全升压信号被传送到泵电路的输出，并且不会被通过门电路的阈值电压减小。 该设计的效率使输出电容充电到接近升压信号平均值的值。

公开(公告)号：US5923613A

公开(公告)日：1999-07-13

申请号：US40435

申请日：1998-03-18

Applicant: Li-Chin Tien ,  Gyh-Bin Wang

Inventor： Li-Chin Tien ,  Gyh-Bin Wang

IPC: G11C7/22 ,  G11C8/00

CPC classification number: G11C7/22

Abstract: A multiple phase latched type synchronized clock circuit that will create a multiple phases of an internal clock signal in an integrated circuit that is synchronized with an external system clock signal is disclosed. A latched type clock synchronizer circuit has an input buffer circuit to receive the external input clock to create a first timing clock. The input buffer is connected to a delay monitor circuit to delay the first timing clock by a first delay factor to create a second timing clock. A delay measurement latch array is connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal, which indicates a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock. A multiple delay array is connected to the input buffer to receive the first timing clock and will create multiple pluralities of incrementally delayed timing clocks. The multiple pluralities of incrementally delay timing clocks and the latched measurement signal are the inputs to a plurality of phase generators that create a plurality of third timing clocks. Each of a plurality of internal buffers is connected to each of the phase generators to receive one of the third timing clocks. The third timing clock is shaped to create one of the multiple phases of the internal clocks which are then buffered, amplified and transmitted to the integrated circuit.

Abstract translation: 公开了一种多相锁存型同步时钟电路，其将在与外部系统时钟信号同步的集成电路中产生内部时钟信号的多个相位。 锁存型时钟同步器电路具有输入缓冲电路，用于接收外部输入时钟以产生第一定时时钟。 输入缓冲器连接到延迟监视器电路，以将第一定时时钟延迟第一延迟因子以产生第二定时时钟。 延迟测量锁存阵列连接到输入缓冲器电路和延迟监视电路，以产生锁存的测量信号，其表示第一定时时钟的第二脉冲与第二定时时钟的第一脉冲之间的一段时间。 多个延迟阵列连接到输入缓冲器以接收第一定时时钟，并且将产生多个递增延迟的定时时钟。 多个增量延迟定时时钟和锁存的测量信号是产生多个第三定时时钟的多个相位发生器的输入。 多个内部缓冲器中的每一个连接到每个相位发生器以接收第三定时时钟中的一个。 第三定时时钟被形成为产生内部时钟的多个相位中的一个，然后被缓冲，放大并传输到集成电路。

公开(公告)号：US10978377B2

公开(公告)日：2021-04-13

申请号：US16732771

申请日：2020-01-02

Applicant: Gyh-Bin Wang

Inventor： Gyh-Bin Wang

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor chip set with double-sided off-chip bonding structure in the disclosure comprises at least one first off-chip bonding structure formed above a first surface of the semiconductor chip set, and at least one second off-chip bonding structure formed above a second surface of the semiconductor chip set, wherein the first surface is opposite to the second surface and each of the first off-chip bonding structure and the second off-chip bonding structure is used for connecting to an electrical connecting point external to the semiconductor chip set through bonding wire, through-silicon via (TSV) or micro bump.

公开(公告)号：US20120229146A1

公开(公告)日：2012-09-13

申请号：US13410472

申请日：2012-03-02

Applicant: Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

Inventor： Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

IPC: G01R27/28

CPC classification number: G01R31/31932 ,  G01R31/31727 ,  G11C29/022 ,  G11C29/50012

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract translation: 高速测试电路从测试仪接收测试仪时钟，并对被测电路进行测试。 高速测试电路根据测试仪时钟产生高频时钟，因此能够在两个频率下工作。 高速测试电路根据高频时钟测试被测电路，并根据例如测试仪时钟的低频时钟执行低速运行。

公开(公告)号：US06229726B1

公开(公告)日：2001-05-08

申请号：US09498742

申请日：2000-02-07

Applicant: Gyh-Bin Wang ,  Chih-Tung Wang ,  Tah-Kang Joseph Ting

Inventor： Gyh-Bin Wang ,  Chih-Tung Wang ,  Tah-Kang Joseph Ting

IPC: G11C502

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1048 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit formed on a semiconductor substrate having multiple input/output signal paths such that the semiconductor substrate can be mounted to more than one package type. The integrated circuit formed on the semiconductor substrate has at least three pluralities of input output connector pads. The first plurality of input/output connector pads is placed on the semiconductor substrate and is attached to a first functional circuit of the integrated circuit. The second and third pluralities of input/output connector pads are placed on the semiconductor substrate and are attached to a second functional circuit of the integrated circuit. The third plurality of input/output connector pads is placed in an area separated from the first and second pluralities of input/output connector pads. Each input/output connector pads of the third plurality of input/output connector pads is connected to a corresponding input/output connector pad of the second plurality of input/output connector pads and thus to the second functional circuit. If the semiconductor substrate is mounted in a first package type, the second plurality of input/output connector pads is bonded to pins of the first package type to connect the second functional circuit to the external circuit, and the third plurality of input/output connector pads remain unbonded. If the semiconductor substrate is mounted in a second package type, the third plurality of input/output connector pads is bonded to pins of the second package type to connect the second functional circuit to the external circuit and the second plurality of input/output connector pads remain unbonded.

Abstract translation: 一种形成在具有多个输入/输出信号路径的半导体衬底上的集成电路，使得半导体衬底可以安装到多于一种封装形式。 形成在半导体衬底上的集成电路具有至少三个输入输出连接器焊盘。 第一组多个输入/输出连接器焊盘被放置在半导体衬底上并且被附接到集成电路的第一功能电路。 第二和第三多个输入/输出连接器焊盘放置在半导体衬底上，并附接到集成电路的第二功能电路。 第三多个输入/输出连接器焊盘放置在与第一和第二多个输入/输出连接器焊盘分离的区域中。 第三多个输入/输出连接器焊盘的每个输入/输出连接器焊盘连接到第二多个输入/输出连接器焊盘的相应输入/输出连接器焊盘，并且因此连接到第二功能电路。 如果半导体衬底被安装在第一封装类型中，则第二多个输入/输出连接器焊盘接合到第一封装类型的引脚，以将第二功能电路连接到外部电路，并且第三多个输入/输出连接器 垫片保持未粘合。 如果半导体衬底被安装在第二封装类型中，则第三个多个输入/输出连接器焊盘接合到第二封装类型的引脚，以将第二功能电路连接到外部电路，而第二个多个输入/输出连接器焊盘 保持未粘合

公开(公告)号：US6130853A

公开(公告)日：2000-10-10

申请号：US50216

申请日：1998-03-30

Applicant: Ming-Hung Wang ,  Gyh-Bin Wang ,  Chun Shiah

Inventor： Ming-Hung Wang ,  Gyh-Bin Wang ,  Chun Shiah

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/00

CPC classification number: G11C7/1015 ,  G11C7/1018 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/10

Abstract: Circuits and a method are disclosed for a semiconductor memory which decode from a system supplied input address two outputs which are either adjacent or boundary adjacent to each other. The two decoded outputs derived from the input address select then, in one cycle, two locations in a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The circuits producing the two decoded outputs allow for sequential and interleaved mode, for data bursts of various lengths, and for addressing of redundant columns.

Abstract translation: 公开了一种半导体存储器的电路和方法，该半导体存储器从系统提供的输入地址中解码两个相邻或相邻边界的输出。 从输入地址导出的两个解码输出在一个周期中选择双倍数据速率同步动态随机存取存储器（DDR SDRAM）中的两个位置。 产生两个解码输出的电路允许顺序和交错模式，用于各种长度的数据突发以及冗余列的寻址。

公开(公告)号：US6064613A

公开(公告)日：2000-05-16

申请号：US221964

申请日：1998-12-28

Applicant: Gyh-Bin Wang

Inventor： Gyh-Bin Wang

IPC: G11C7/06 ,  G11C7/02

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A fast CMOS sense amplifier for semiconductor memories is disclosed. The memory sense amplifier configuration is comprised of differential pre-sense amplifier stage and a sense amplifier second stage. The pre-sense amplifier stage is composed of two sections with feedback between the sections which reduces the output swing by means of a clamping action, therefore improving output switching recovery time in response to differential input. The feedback between the sections is provided by cross connecting the sub outputs of each section to the gate of a clamping transistor at each section. The reduced recovery time produces reduced delay at the output which speeds up the operation of the sense amplifier. Additionally, the clamping devices have the effect of reducing the average DC current in the pre-sense amplifier.

Abstract translation: 公开了一种用于半导体存储器的快速CMOS读出放大器。 存储器读出放大器配置包括差分预读放大器级和读出放大器第二级。 预读放大器级由两部分组成，其中部分之间具有反馈，借助于钳位动作来减小输出摆幅，从而根据差分输入改善输出开关恢复时间。 各部分之间的反馈通过将每个部分的子输出交叉连接到每个部分的钳位晶体管的栅极来提供。 缩短的恢复时间在输出端产生减小的延迟，从而加速读出放大器的工作。 此外，钳位装置具有减小预读放大器中的平均直流电流的效果。