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    Set-reset latches
    11.
    发明授权
    Set-reset latches 有权

    公开(公告)号：US10075150B2

    公开(公告)日：2018-09-11

    申请号：US15227326

    申请日：2016-08-03

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Christopher Allan Poirier ,  Ryan Barnhill ,  Dacheng Zhou

    IPC: H03K3/356

    CPC classification number: H03K3/356121 ,  H03K3/356113

    Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

    Capacitor voltage stacking pipeline analog-to-digital converter (ADC)
    12.
    发明授权
    Capacitor voltage stacking pipeline analog-to-digital converter (ADC) 有权

    公开(公告)号：US11265007B2

    公开(公告)日：2022-03-01

    申请号：US16938856

    申请日：2020-07-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Peter Kurahashi ,  Dacheng Zhou ,  Michael James Marshall

    IPC: H03M1/16 ,  H03M1/12

    Abstract: Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.

    METHODS AND APPARATUS TO GENERATE A CIRCUIT PROTECTION VOLTAGE
    13.
    发明申请
    METHODS AND APPARATUS TO GENERATE A CIRCUIT PROTECTION VOLTAGE 审中-公开

    公开(公告)号：US20190199339A1

    公开(公告)日：2019-06-27

    申请号：US15853215

    申请日：2017-12-22

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dacheng Zhou

    IPC: H03K17/08 ,  G06F1/32

    Abstract: Apparatus, methods and systems to produce a protection voltage are disclosed. The apparatus includes circuitry to deliver a first supply voltage to a plurality of circuits, where the first supply voltage has a first magnitude, circuitry to deliver a second supply voltage to a part of the plurality of circuits, where the second supply voltage has a second magnitude, and circuitry to deliver a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH. The protection voltage has a magnitude that is a fraction of the magnitude of the first supply voltage. The apparatus includes circuitry that causes the delivery of the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

    METHOD AND SYSTEM FOR IMPROVING ANALOG-TO-DIGITAL CONVERSION PERFORMANCE
    15.
    发明公开
    METHOD AND SYSTEM FOR IMPROVING ANALOG-TO-DIGITAL CONVERSION PERFORMANCE 审中-公开

    公开(公告)号：US20240204789A1

    公开(公告)日：2024-06-20

    申请号：US18081490

    申请日：2022-12-14

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi ,  Ryan Barnhill ,  Michael James Marshall

    IPC: H03M1/06

    CPC classification number: H03M1/0607

    Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

    Set-reset latches
    16.
    发明授权
    Set-reset latches 有权

    公开(公告)号：US11201607B2

    公开(公告)日：2021-12-14

    申请号：US16121570

    申请日：2018-09-04

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Christopher Allan Poirier ,  Ryan Barnhill ,  Dacheng Zhou

    IPC: H03K3/356

    Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

    SET-RESET LATCHES
    18.
    发明申请
    SET-RESET LATCHES 审中-公开

    公开(公告)号：US20180375501A1

    公开(公告)日：2018-12-27

    申请号：US16121570

    申请日：2018-09-04

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Christopher Allan Poirier ,  Ryan Barnhill ,  Dacheng Zhou

    IPC: H03K3/356

    Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

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