公开(公告)号：US07333789B2

公开(公告)日：2008-02-19

申请号：US10529539

申请日：2004-08-04

申请人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

发明人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

IPC分类号： H04B1/18

CPC分类号： H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

摘要： A broadband modulation PLL includes a PLL portion containing a voltage controlled oscillator (101), a frequency divider (105), a phase comparator (104) and a loop filter (103). A frequency-dividing ratio of the frequency divider (105) is controlled to apply modulation, and also an input voltage of the voltage controlled oscillator (101) is controlled to apply modulation. One of phase modulation data for controlling the frequency dividing ratio and phase modulation data for input voltage of the voltage controlled oscillator (101) is inverted in phase by using an inverter (113), and the delay control circuit (110) detects a timing error on the basis of a signal (133) achieved by adding the output signals (131) and (132) of the filter (106) and the loop filter (103), and the timing is controlled by the delay circuits (111) and (112) to correct, the timing error.

摘要翻译： 宽带调制PLL包括包含压控振荡器（101），分频器（105），相位比较器（104）和环路滤波器（103）的PLL部分。 控制分频器（105）的分频比来施加调制，并且控制压控振荡器（101）的输入电压以进行调制。 用于控制压控振荡器（101）的输入电压的分频比和相位调制数据的相位调制数据之一通过使用逆变器（113）而相位反相，延迟控制电路（110）检测定时误差 基于通过将滤波器（106）和环路滤波器（103）的输出信号（131）和（132）相加而获得的信号（133），并且由延迟电路（111）和（ 112）纠正，定时错误。

公开(公告)号：US20070019759A1

公开(公告)日：2007-01-25

申请号：US10573816

申请日：2004-09-27

申请人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

发明人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

IPC分类号： H03D3/00

CPC分类号： H04L27/36

摘要： An amplitude information extraction apparatus capable of reducing an amplitude error with a smaller circuit scale than theoretical operation circuits. In this apparatus, amplitude information extraction apparatus (110) acquires amplitude information (amplitude value Z′) to be corrected from an I component and Q component of a transmission signal. Phase information extraction apparatus (111) acquires phase information from an I component and Q component of the transmission signal. Amplitude information extraction apparatus (110) then acquires amplitude value Z by correcting the acquired amplitude information (amplitude value Z′) based on the phase information acquired by phase information extraction apparatus (111).

摘要翻译： 一种振幅信息提取装置，其能够以比理论运算电路更小的电路尺寸来减小振幅误差。 在该装置中，振幅信息提取装置（110）从发送信号的I分量和Q分量获取要校正的幅度信息（振幅值Z'）。 相位信息提取装置（111）从发送信号的I分量和Q分量获取相位信息。 幅度信息提取装置（110）然后通过基于由相位信息提取装置（111）获取的相位信息校正获取的幅度信息（振幅值Z'）来获得振幅值Z。

公开(公告)号：US20100073095A1

公开(公告)日：2010-03-25

申请号：US12566347

申请日：2009-09-24

申请人： Shunsuke Hirano

发明人： Shunsuke Hirano

IPC分类号： H03L7/085

CPC分类号： H03L7/18 ,  H03L7/085 ,  H03L7/185 ,  H03L2207/12

摘要： A frequency synthesizer (100) can selectively set an output band of VCO, and consumes less power. The frequency synthesizer (100) has a frequency converting circuit (110) that has a mixer (111) and a frequency divider (112) connected with each other in parallel. The frequency synthesizer (100) uses the frequency divider (112) upon frequency band selection in VCO (101) and uses the mixer (111) upon transmission.

摘要翻译： 频率合成器（100）可以选择性地设置VCO的输出频带，并且消耗更少的功率。 频率合成器（100）具有频率转换电路（110），其具有并联连接的混频器（111）和分频器（112）。 频率合成器（100）在VCO（101）中进行频带选择时使用分频器（112），并且在发送时使用混频器（111）。

公开(公告)号：US07236063B2

公开(公告)日：2007-06-26

申请号：US10539426

申请日：2004-07-22

申请人： Taketoshi Ochi ,  Shunsuke Hirano

发明人： Taketoshi Ochi ,  Shunsuke Hirano

IPC分类号： H03B5/00

CPC分类号： H03C3/0991 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/197 ,  H03L2207/06

摘要： A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

摘要翻译： 本发明的一个问题是以低成本提供具有良好调制精度的宽带调制PLL。 对于具有VCO（21），分频器（22），相位比较器（23），电荷泵（24）和环路滤波器（25）的PLL，VCO（21）和分频比 控制分频器（22）进行调制。 VCO（21）具有用于PLL和调制的两个控制端子，并且控制信号生成部件（28）基于相位调制数据和输入端产生VCO（21）的控制电压V tm 电压V L1到PLL的控制端子。 在调整调制因子时，控制用于调制VCO（21）的控制端子的控制电压V SUB，并且输入电压V SUB1是 并且计算VCO（21）的频率到V tm的调制灵敏度，并且基于所获得的调制灵敏度来调整相位调制数据的调制系数。

公开(公告)号：US20060115036A1

公开(公告)日：2006-06-01

申请号：US11333245

申请日：2006-01-18

申请人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

发明人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

IPC分类号： H03D3/24

CPC分类号： H03L7/1976

摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

摘要翻译： 包括PLL电路的频率合成器装置的分数部分控制电路是用于控制与PLL电路的可变分频器分频的分数部分的多n-Δ级Δ-Σ调制器电路。 加法器将分数部分的数据与来自乘法器的输出数据相加，并将结果数据通过二阶积分器输出到量化器。 量化器用量化步长量化输入数据，并通过反馈电路将量化的数据输出到乘法器。 量化数据用作受控分数部分的数据。 乘法器将来自反馈电路的数据乘以量化步长，并将结果数据输出到加法器。 分数部分控制电路周期性地改变分数部分的数据，从而根据周期的平均值设置来自VCO的输出信号的频率。

公开(公告)号：US06728526B2

公开(公告)日：2004-04-27

申请号：US09794185

申请日：2001-02-26

申请人： Ryoichi Yamada ,  Shunsuke Hirano ,  Yasunori Miyahara ,  Hisashi Adachi ,  Hisashi Takahashi ,  Hiroki Kojima

发明人： Ryoichi Yamada ,  Shunsuke Hirano ,  Yasunori Miyahara ,  Hisashi Adachi ,  Hisashi Takahashi ,  Hiroki Kojima

IPC分类号： H04B106

CPC分类号： H03L7/1976

摘要： A frequency synthesizer device comprising a PLL circuit (9) and a frequency-division ratio control circuit (5). The PLL circuit (9) includes a phase comparator (1), a low-pass filter (2), a voltage-controlled oscillator (3), and a variable frequency divider (4). The frequency-division ratio control circuit (5) controls the variable frequency divider (4) such that a frequency division ratio of the variable frequency divider (4) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider (4) and an output fdiv2 obtained via a delay element (10) are used as clocks of an accumulator portion (81) in the frequency-division ratio control circuit (5). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit (5) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.

摘要翻译： 一种频率合成器装置，包括PLL电路（9）和分频比控制电路（5）。 PLL电路（9）包括相位比较器（1），低通滤波器（2），压控振荡器（3）和可变分频器（4）。 分频比控制电路（5）控制可变分频器（4），使得可变分频器（4）的分频比在时间上变化，并且分频比的时间平均值包含低于 小数点。 使用分频比控制电路（5）中的可变分频器（4）的输出信号fdiv和通过延迟元件（10）获得的输出fdiv2的两个不同信号作为累加器部分（81）的时钟， 。 可以减小由分频比控制电路（5）的操作产生的基板电位的变化和电源电压的变化，并且可以抑制频率合成器的C / N的劣化。

公开(公告)号：US20130148769A1

公开(公告)日：2013-06-13

申请号：US13816156

申请日：2012-02-06

申请人： Shunsuke Hirano

发明人： Shunsuke Hirano

IPC分类号： H04L7/033

CPC分类号： H04L7/033 ,  H03L7/0805 ,  H03L7/18

摘要： A wireless apparatus includes a clock generation PLL circuit of a digital baseband section. A variable output regulator receives as an input a VCO control voltage for controlling an oscillation frequency of a VCO in the PLL circuit, varies an output voltage in accordance with the VCO control voltage, and supplies, as a supply voltage, the output voltage to a power terminal of a high frequency circuit, such as an amplifier. The VCO control voltage changes in accordance with temperature or process variations, and the supply voltage of the high frequency circuit is controlled in accordance with the VCO control voltage. For this reason, performance deterioration ascribable to the temperature or process variations can be compensated for.

摘要翻译： 无线装置包括数字基带部分的时钟产生PLL电路。 可变输出调节器接收用于控制PLL电路中的VCO的振荡频率的VCO控制电压作为输入，根据VCO控制电压改变输出电压，并将输出电压作为电源电压提供给 高频电路的电源端子，如放大器。 VCO控制电压根据温度或工艺变化而变化，高频电路的电源电压根据VCO控制电压进行控制。 为此，可以补偿归因于温度或工艺变化的性能劣化。

公开(公告)号：US07215215B2

公开(公告)日：2007-05-08

申请号：US11078703

申请日：2005-03-14

申请人： Shunsuke Hirano ,  Hisashi Adachi

发明人： Shunsuke Hirano ,  Hisashi Adachi

IPC分类号： H03C3/06

CPC分类号： H03C3/0983 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095

摘要： A phase modulation apparatus is provided whereby excellent RF phase modulation signals can be obtained even when the modulation sensitivity of a voltage controlled oscillator varies. Phase modulation apparatus 100 has: phase detector 105 that performs phase detection with respect to an RF phase modulation signal outputted from VCO 101; comparator 106 that compares the phase of the detected signal with the phase of a baseband phase modulation signal and outputs the difference between the signals; variable gain amplifier 107 that controls the gain of the baseband phase modulation signal based on the output of comparator 106 and supplies the gain-controlled baseband phase modulation signal to VCO 101. By this means, the signal level of the baseband phase modulation signal that is supplied to VCO 101 can be controlled in accordance with the modulation sensitivity of VCO 101, so that phase modulation apparatus 100 can be realized whereby excellent RF phase modulation signals even when the modulation sensitivity of VCO 101 varies.

摘要翻译： 提供一种相位调制装置，即使当压控振荡器的调制灵敏度变化时，也可以获得优异的RF相位调制信号。 相位调制装置100具有：相位检测器105，其相对于从VCO101输出的RF相位调制信号进行相位检测; 比较器106，其将检测信号的相位与基带相位调制信号的相位进行比较，并输出信号之间的差; 可变增益放大器107，其基于比较器106的输出来控制基带相位调制信号的增益，并将增益控制的基带相位调制信号提供给VCO101。 通过这种方式，可以根据VCO101的调制灵敏度来控制提供给VCO 101的基带相位调制信号的信号电平，从而可以实现相位调制装置100，从而即使在 VCO 101的调制灵敏度变化。

公开(公告)号：US20060197605A1

公开(公告)日：2006-09-07

申请号：US10568318

申请日：2004-07-21

申请人： Shunsuke Hirano ,  Taketoshi Ochi

发明人： Shunsuke Hirano ,  Taketoshi Ochi

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

摘要： A problem of the invention is to provide a wide band modulation PLL having an excellent modulation accuracy at low cost. With respect to a PLL portion including VCO (21), a divider (22), a phase comparator (23), and a loop filter (24), a dividing ratio of the divider (24) is modulated by a dividing ratio generating portion (29) by controlling a control voltage of VCO (21) by a control signal generating portion (30). VCO (21) includes two control terminals, and the control signal generating portion (30) inputs the control signal to one of the control terminals. In controlling a modulation degree, the dividing ratio generating portion (29) is inputted with a calibration data fc1 and the control signal generating portion (30) is inputted with a calibration data fc2. A demodulator (31) demodulates output signals of VCO (21) when the respective calibration data are inputted and modulation degree controlling means (32) outputs a modulation degree control signal to the control signal generating portion (30) based on the demodulated signals.

摘要翻译： 本发明的一个问题是以低成本提供具有优良调制精度的宽带调制PLL。 对于包括VCO（21），分频器（22），相位比较器（23）和环路滤波器（24）的PLL部分，分频器（24）的分频比由分频比生成部分 （29）通过控制信号产生部分（30）控制VCO（21）的控制电压。 VCO（21）包括两个控制端子，控制信号产生部分（30）将控制信号输入到控制端子之一。 在控制调制度时，分频比产生部分（29）被输入校准数据f c1，并且控制信号产生部分（30）被输入校准数据f c2 < / SUB>。 当输入各个校准数据时，解调器（31）对VCO（21）的输出信号进行解调，并且调制度控制装置（32）基于解调信号将调制度控制信号输出到控制信号产生部分（30）。

公开(公告)号：US06871055B2

公开(公告)日：2005-03-22

申请号：US10218658

申请日：2002-08-15

申请人： Shunsuke Hirano ,  Yasunori Miyahara

发明人： Shunsuke Hirano ,  Yasunori Miyahara

IPC分类号： H04B1/30 ,  H04B1/10

CPC分类号： H04B1/30

摘要： In a direction conversion receiver, a quadrature demodulator produces differential signals in a baseband on the basis of a local signal of a frequency synthesizer, with the differential signals being inputted through a first low pass filter, a gain control amplifier and an amplifier to a control unit and a direct current component between the differential signals being extracted in a second low pass filter. In addition, an offset compensating section reduces an offset voltage while the control unit outputs a control signal for the control of the gain control amplifier. The second low pass filter includes a time constant circuit for determining a time constant through the use of resistors and a capacitor, and a time constant changing section. A time constant control unit controls the time constant changing section for a predetermined period of time after the control unit outputs data for the change of a frequency of the local signal so that the time constant of the time constant circuit decreases. This shortens the time needed for the settlement of automatic gain control and prevents the deterioration of demodulation accuracy during a call.

摘要翻译： 在方向转换接收机中，正交解调器基于频率合成器的本地信号在基带中产生差分信号，差分信号通过第一低通滤波器，增益控制放大器和放大器输入到控制器 单元和在第二低通滤波器中提取的差分信号之间的直流分量。 此外，偏移补偿部分减小偏移电压，同时控制单元输出用于控制增益控制放大器的控制信号。 第二低通滤波器包括用于通过使用电阻器和电容器来确定时间常数的时间常数电路和时间常数变化部分。 时间常数控制单元在控制单元输出用于改变本地信号的频率的数据之后的预定时间段来控制时间常数变化部分，使得时间常数电路的时间常数减小。 这缩短了自动增益控制结算所需的时间，并防止了通话过程中解调精度的恶化。