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    Transistor and method of manufacturing the same
    11.
    发明申请
    Transistor and method of manufacturing the same 审中-公开
    晶体管及其制造方法

    公开(公告)号：US20060038243A1

    公开(公告)日：2006-02-23

    申请号：US11071018

    申请日：2005-03-03

    申请人： Tetsuji Ueno ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Tetsuji Ueno ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66621 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/045 ,  H01L29/165 ,  H01L29/32 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659

    摘要： A transistor of the present invention includes a semiconductor substrate that has a first surface of the {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a side face of the {111} crystal plane connecting the first surface to the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the side face. Impurity regions are formed adjacent to both sides of the gate structure. The impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

    摘要翻译： 本发明的晶体管包括半导体衬底，其具有{100}晶面的第一表面，{100}晶面的第二表面的高度低于第一表面的高度，并且 {111}晶面将第一表面连接到第二表面。 栅极结构形成在第一表面上。 在第二表面和侧面上形成外延层。 杂质区域形成在栅极结构的两侧附近。 杂质区域具有{111}晶面的侧面，从而可以防止在杂质区域之间产生的短沟道效应。

    CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
    13.
    发明授权
    CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
    具有升高的源极和漏极区域的CMOS半导体器件及其制造方法

    公开(公告)号：US07714394B2

    公开(公告)日：2010-05-11

    申请号：US11285978

    申请日：2005-11-23

    申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L23/58

    CPC分类号： H01L29/7834 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

    摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.

    摘要翻译： 提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。

    Methods of fabricating a semiconductor device using a selective epitaxial growth technique
    14.
    发明授权
    Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
    使用选择性外延生长技术制造半导体器件的方法

    公开(公告)号：US07361563B2

    公开(公告)日：2008-04-22

    申请号：US11299447

    申请日：2005-12-09

    申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L21/205 ,  H01L29/80 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

    摘要翻译： 使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。 将具有凹部的基板装入反应室。 将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。 选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

    Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same
    15.
    发明申请
    Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
    在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法

    公开(公告)号：US20050279997A1

    公开(公告)日：2005-12-22

    申请号：US11154236

    申请日：2005-06-16

    申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/336 ,  H01L29/772

    CPC分类号： H01L21/28044 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/66772

    摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.

    摘要翻译： 在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶 半导体图案，分别使用主半导体源气体和主蚀刻气体。 使用选择性蚀刻气体去除非单晶外延半导体层。 主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。 选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    18.
    发明申请
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 有权
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号：US20050023646A1

    公开(公告)日：2005-02-03

    申请号：US10851336

    申请日：2004-05-24

    申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

    摘要： A multi-layered structure of a semiconducotr device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

    Method of fabricating MOS transistor using total gate silicidation process
    19.
    发明授权
    Method of fabricating MOS transistor using total gate silicidation process 失效
    使用全栅极硅化工艺制造MOS晶体管的方法

    公开(公告)号：US07101776B2

    公开(公告)日：2006-09-05

    申请号：US10806301

    申请日：2004-03-22

    申请人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L21/44 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66545

    摘要： There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.

    摘要翻译： 提供了使用总栅极硅化工艺制造MOS晶体管的方法。 该方法包括在半导体衬底上形成绝缘栅极图案。 绝缘栅图案包括依次层叠的硅图案和牺牲层图案。 形成覆盖栅极图案的侧壁的间隔物，并且通过使用间隔物和栅极图案作为离子注入掩模将杂质离子注入到半导体衬底中来形成源极/漏极区域。 通过去除具有源极/漏极区域的半导体衬底上的牺牲层图案来暴露硅图案。 暴露的硅图案完全转换为栅极硅化物层，并且同时在源极/漏极区域的表面上选择性地形成源极/漏极硅化物层。

    Transistors having reinforcement layer patterns and methods of forming the same
    20.
    发明申请
    Transistors having reinforcement layer patterns and methods of forming the same 有权
    具有加强层图案的晶体管及其形成方法

    公开(公告)号：US20060038200A1

    公开(公告)日：2006-02-23

    申请号：US11204564

    申请日：2005-08-15

    申请人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

    IPC分类号： H01L31/0328 ,  H01L21/336

    CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834

    摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.

    摘要翻译： 根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。 晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。 最后，在半导体衬底的有源区上设置至少一个栅极图案。 加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。 每个加强层图案部分地暴露栅极图案的每个侧壁。 杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。 间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。