公开(公告)号：US07002503B2

公开(公告)日：2006-02-21

申请号：US10977954

申请日：2004-10-29

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： H03M1/36

CPC分类号： H03M7/165 ,  H03M7/22

摘要： A binary encoder which has a fast conversion speed, occupies a small area, and consumes a small amount of power is provided. The binary encoder includes first and second latch transistors, first and second charge transistors, first and second control transistors, first and second discharge transistors, an equalize transistor, and first and second inverters. The first charge transistor charges a first output node to a level of a power voltage in response to a clock signal. The second charge transistor charges a second output node to the level of the power voltage in response to the clock signal. The first discharge transistor discharges a first control node to a level of a ground voltage in response to a first input signal. The second discharge transistor discharges a second control node to the level of the ground voltage in response to a second input signal.

摘要翻译： 具有快速转换速度的二进制编码器占用小面积，并且消耗少量的功率。 二进制编码器包括第一和第二锁存晶体管，第一和第二充电晶体管，第一和第二控制晶体管，第一和第二放电晶体管，均衡晶体管以及第一和第二反相器。 第一充电晶体管响应于时钟信号将第一输出节点充电到电源电压的电平。 第二充电晶体管响应于时钟信号而将第二输出节点充电到电源电压的电平。 第一放电晶体管响应于第一输入信号将第一控制节点放电至接地电压的电平。 第二放电晶体管响应于第二输入信号将第二控制节点放电到接地电压的电平。

公开(公告)号：US20050051605A1

公开(公告)日：2005-03-10

申请号：US10959100

申请日：2004-10-07

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： B23K3/06 ,  H01L21/56 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34 ,  B23K31/02

CPC分类号： H05K3/3436 ,  B23K3/0607 ,  B23K3/0623 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15787 ,  H05K2201/10424 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

摘要： A process of manufacturing a solder-fill is comprised of: arranging a plurality of wire or rod shaped solder bump material to match with the connection pattern of semiconductor chip and PCB in a container, filling a liquid state of under-fill material into the container, solidifying the under-fill material in the container, and slicing the solidified under-fill material and solder bump material with a uniform thickness.

摘要翻译： 制造焊料填充的过程包括：将多个线或棒状焊料凸块材料布置成与容器中的半导体芯片和PCB的连接图案相匹配，将未填充材料的液态填充到容器中 固化容器中的填充不足的材料，并将均匀厚度的固化后的填充材料和焊料凸块材料切片。

公开(公告)号：US5784131A

公开(公告)日：1998-07-21

申请号：US733095

申请日：1996-10-16

申请人： Hong-Gyu Kim ,  Kyung-Seob Han ,  Ho-Young Lee

发明人： Hong-Gyu Kim ,  Kyung-Seob Han ,  Ho-Young Lee

IPC分类号： G02F1/133 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/13 ,  G02F1/136

CPC分类号： G02F1/136213 ,  G02F1/1368 ,  G02F1/136227

摘要： Method for fabricating a liquid crystal display, is disclosed, including the steps of forming a first semiconductor layer in a thin film transistor region on a substrate and forming a second semiconductor layer in a storage capacitor region on the substrate, forming a gate insulating film on the first, and second semiconductor layers and forming a gate electrode over the first semiconductor layer in the thin film transistor region, injecting impurity ions into entire surface of the substrate using the gate electrode as a mask in forming a source region and a drain region in the first semiconductor layer, forming a first interlayer insulating film on entire surface of the substrate including the gate electrode and forming a first contact hole such that the first contact hole exposes the source region, forming a data line on a part of the first interlayer insulating film such that the data line is connected to the source region through the first contact hole, forming a second interlayer insulating film on entire surface of the substrate including the data line and forming second, third contact holes such that the second, and third contact holes expose the gate insulating film on the second semiconductor layer and the drain region respectively and forming a pixel electrode on the second interlayer insulating film such that the pixel electrode is connected to the gate insulating film on the second semiconductor layer and the drain region through the second and third contact holes respectively and forming a protection film on entire surface including the pixel electrode, whereby a numerical aperture can be improving allowing improvement of picture quality.

摘要翻译： 公开了一种用于制造液晶显示器的方法，包括以下步骤：在衬底上的薄膜晶体管区域中形成第一半导体层，并在衬底上的保持电容器区域中形成第二半导体层，形成栅绝缘膜 第一半导体层和第二半导体层，并且在薄膜晶体管区域中的第一半导体层上形成栅电极，使用栅电极作为掩模将杂质离子注入到基板的整个表面中，以形成源极区域和漏极区域 所述第一半导体层在包括所述栅电极的所述基板的整个表面上形成第一层间绝缘膜，并形成第一接触孔，使得所述第一接触孔暴露所述源极区，在所述第一层间绝缘部分的一部分上形成数据线 使得数据线通过第一接触孔连接到源极区域，形成第二中间层 在包括数据线的基板的整个表面上形成绝缘膜，并形成第二和第三接触孔，使得第二和第三接触孔分别在第二半导体层和漏极区域上暴露栅极绝缘膜，并在其上形成像素电极 第二层间绝缘膜，使得像素电极分别通过第二和第三接触孔与第二半导体层和漏极区域上的栅极绝缘膜连接，并且在包括像素电极的整个表面上形成保护膜，由此数值孔径 可以提高图像质量。

公开(公告)号：US08229213B2

公开(公告)日：2012-07-24

申请号：US12307068

申请日：2007-07-25

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： G06K9/00

CPC分类号： H04N9/045 ,  H04N9/646 ,  H04N2209/046

摘要： A color interpolation method and a device are disclosed. The color interpolation method includes (a) setting a grid noise coefficient; (b) computing a grid noise offset by using the grid noise coefficient set in the step of (a); (c) extracting a pixel value only from a Bayer pattern image regardless of R, G and B values and computing edge directional information; (d) determining a condition of the edge directional information, computed in the step of (b), among a plurality of predetermined conditions, each of the plurality of predetermined conditions corresponding to a color interpolation parameter computing algorithm and the grid noise offset being used as a parameter of the color interpolation parameter computing algorithm corresponding to each of the conditions; and (e) computing a color interpolation parameter based on the color interpolation parameter computing algorithm corresponding to the condition of the edge directional information, determined in the step of (d).

摘要翻译： 公开了彩色插值方法和装置。 颜色插值方法包括（a）设置网格噪声系数; （b）通过使用在（a）的步骤中设定的网格噪声系数来计算网格噪声偏移; （c）仅从Bayer图案图像提取像素值，而不管R，G和B值如何，并计算边缘方向信息; （d）确定在步骤（b）中计算出的边缘方向信息的条件，在多个预定条件中，与颜色插值参数计算算法相对应的多个预定条件中的每一个和使用的网格噪声偏移 作为与每个条件对应的颜色插值参数计算算法的参数; 以及（e）基于与（d）的步骤中确定的边缘方向信息的条件相对应的颜色插值参数计算算法计算颜色插值参数。

公开(公告)号：US20120102654A1

公开(公告)日：2012-05-03

申请号：US13317314

申请日：2011-10-14

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： A47G9/10 ,  A47G9/02

CPC分类号： A47G9/0253 ,  A47G2009/1018

摘要： Disclosed is a pillow whose inner portion is constructed of two layers, an upper layer which is in contact with a user's head having a functional material such as a bead foam therein and a lower layer which is in contact with a floor or the bottom having a cushion member such as cotton, latex foam, and memory foam therein, so that the pillow has an advantage of the functional material, thereby increasing a user's health and has no difficulty of keeping a shape, thereby obtaining an excellent supportability, having a good cushion feeling and saving cost.

摘要翻译： 公开了一种枕头，其内部部分由两层构成，上层与使用者的头部接触，所述使用者的头部具有诸如其中的珠粒泡沫的功能性材料，以及与地板接触的下层或具有 缓冲构件如棉，乳胶泡沫和记忆泡沫，使得枕头具有功能材料的优点，从而增加使用者的健康，并且不难保持形状，从而获得优异的支撑性，具有良好的缓冲 感觉和节省成本。

公开(公告)号：US20110157135A1

公开(公告)日：2011-06-30

申请号：US12982068

申请日：2010-12-30

申请人： Ho-Young Lee ,  Nam-Kil Park

发明人： Ho-Young Lee ,  Nam-Kil Park

IPC分类号： G09G5/00 ,  G09G3/30

CPC分类号： G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/0297 ,  G09G2310/061 ,  G09G2320/0238

摘要： An OLED display device for improving a contrast ratio is disclosed. The OLED display device includes a pixel circuit, wherein the pixel circuit includes a driving transistor driving the light emitting device, a first switching transistor supplying a data voltage from a data line to a first node in response to a first scan signal from a first scan line, a second switching transistor connecting the driving transistor to a power line in a diode structure in response to the first scan signal from the first scan line, a third switching transistor supplying a reference voltage from a reference voltage supply line to the first node in response to a light emission control signal from a light emission control line, a fourth switching transistor connecting the driving transistor to the light emitting device in response to the light emission control signal from the light emission control line, a fifth switching transistor connecting the fourth switching transistor to the reference voltage supply line in response to a second scan signal from the second scan line, a storage capacitor connected between the first node and a second node connected to a gate electrode of the driving transistor, and a boost capacitor connected to the first scan line and the second node.

摘要翻译： 公开了一种用于提高对比度的OLED显示装置。 OLED显示装置包括像素电路，其中像素电路包括驱动发光器件的驱动晶体管，响应于来自第一扫描的第一扫描信号而将数据电压从数据线提供给第一节点的第一开关晶体管 线路，响应于来自第一扫描线的第一扫描信号而将驱动晶体管连接到二极管结构中的电力线的第二开关晶体管，将参考电压从参考电压供应线路提供给第一节点的第三开关晶体管， 响应于来自发光控制线的发光控制信号，第四开关晶体管，响应于来自发光控制线的发光控制信号将驱动晶体管连接到发光器件;第五开关晶体管，连接第四开关 晶体管响应于来自第二扫描线的第二扫描信号到参考电压供应线， 连接在第一节点和连接到驱动晶体管的栅电极的第二节点之间的存储电容器，以及连接到第一扫描线和第二节点的升压电容器。

公开(公告)号：US07554470B2

公开(公告)日：2009-06-30

申请号：US11982747

申请日：2007-11-05

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： H03M1/10

CPC分类号： H03M1/1042 ,  H03M1/069 ,  H03M1/44

摘要： A pipeline analog-to-digital converter (ADC) having a digital calibrating circuit is described. The pipeline ADC includes a pipeline converting circuit and a digital calibrating circuit. The pipeline converting circuit has a plurality of one-bit stages, and converts an analog input signal into a first digital signal having a plurality of bits. The digital calibrating circuit extracts calibration coefficients for the one-bit stages, and calibrates a feedback signal based on the calibration coefficients and the first digital signal to generate a second digital signal having a plurality of bits. The pipeline ADC may perform digital calibration automatically with good linearity.

摘要翻译： 描述了具有数字校准电路的管线模数转换器（ADC）。 流水线ADC包括流水线转换电路和数字校准电路。 流水线转换电路具有多个一比特级，并且将模拟输入信号转换为具有多个比特的第一数字信号。 数字校准电路提取一比特级的校准系数，并且基于校准系数和第一数字信号校准反馈信号以产生具有多个比特的第二数字信号。 流水线ADC可以以良好的线性度自动执行数字校准。

公开(公告)号：US20090010561A1

公开(公告)日：2009-01-08

申请号：US12159386

申请日：2006-09-15

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： G06K9/40

CPC分类号： G06T5/002

摘要： A device for removing noise by using an adjustable threshold. The device for removing noise in accordance with an embodiment of the present invention determines a difference value between a maximum value and a minimum value of elements of inputted image data, determines a method of removing noise of the image data in accordance with the difference value, and removes noise in accordance with the method. With the present invention, improved picture quality can be achieved because noise can be removed as desired by the user.

摘要翻译： 用于通过使用可调阈值去除噪声的装置。 根据本发明的实施例的用于去除噪声的装置确定输入图像数据的元素的最大值和最小值之间的差值，根据差值确定去除图像数据的噪声的方法， 并根据该方法去除噪声。 利用本发明，由于可以根据用户的需要去除噪声，因此可以实现改进的图像质量。

公开(公告)号：US20080303953A1

公开(公告)日：2008-12-11

申请号：US12159384

申请日：2006-05-26

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： H04N5/00

CPC分类号： H04N9/045 ,  H04N5/3658

摘要： A device and a method for removing grid noises are disclosed. The device for removing grid noises in accordance with an embodiment of the present invention calculates an average value of each line of an inputted Bayer pattern image, calculates an estimate value estimating an average of even number lines placed between the odd number lines of a Bayer pattern image and odd number lines placed between the even number lines of a Bayer pattern image, calculates a difference value between the estimate value and the average value, calculates a correction coefficient by using the difference value, and applies the correction coefficient to the Bayer pattern image and outputs a corrected Bayer pattern image.

摘要翻译： 公开了一种用于去除网格噪声的装置和方法。 根据本发明的实施例的用于去除网格噪声的装置计算输入拜耳图案图像的每行的平均值，计算估计放置在拜耳图案的奇数行之间的偶数行的平均值的估计值 放置在拜耳图案图像的偶数行之间的图像和奇数行计算估计值和平均值之间的差值，通过使用差值计算校正系数，并将校正系数应用于拜耳图案图像 并输出校正的拜耳图案图像。

公开(公告)号：US20060006920A1

公开(公告)日：2006-01-12

申请号：US11222107

申请日：2005-09-08

申请人： Ho-Young Lee

发明人： Ho-Young Lee

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： Described is a level shifting device for high-frequency operation. The level shifting device includes first through fifth transistors. The first transistor has its gate connected to an input signal, its source connected to the voltage node at an lower voltage value, and its drain connected to an output signal. The second transistor has its gate connected to an inverted version of the input signal, its source connected to the voltage node at the lower voltage value, and its drain connected to an inverted version of the output signal. The third transistor has its gate connected to the drain of the second transistor and its drain connected to the drain of the first transistor. The fourth transistor has its gate connected to the drain of the first transistor, its drain connected to the drain of the second transistor, and its source connected to the voltage supply at an first upper voltage value. The fifth transistor has its gate connected to the input signal, its source connected to the voltage supply at the first upper voltage value, and its drain connected to the source of the third transistor. The input signal swings between a second upper voltage value and the lower voltage value and the output signal swings between the first upper voltage value and the lower voltage value.

摘要翻译： 描述了用于高频操作的电平移位装置。 电平移位装置包括第一至第五晶体管。 第一晶体管的栅极连接到输入信号，其源极以较低的电压值连接到电压节点，其漏极连接到输出信号。 第二晶体管的栅极连接到输入信号的反相形式，其源极以较低的电压值连接到电压节点，其漏极连接到反相型输出信号。 第三晶体管的栅极连接到第二晶体管的漏极，其漏极连接到第一晶体管的漏极。 第四晶体管的栅极连接到第一晶体管的漏极，其漏极连接到第二晶体管的漏极，其源极以第一高电压值连接到电压源。 第五晶体管的栅极连接到输入信号，其源极以第一高电压值连接到电压源，其漏极连接到第三晶体管的源极。 输入信号在第二高电压值和较低电压值之间摆动，并且输出信号在第一高电压值和较低电压值之间摆动。