公开(公告)号：US20070109872A1

公开(公告)日：2007-05-17

申请号：US11380662

申请日：2006-04-28

申请人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Shih-Jye Shen ,  Ya-Chin King ,  Ching-Hsiang Hsu

发明人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Shih-Jye Shen ,  Ya-Chin King ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/6656 ,  H01L29/7881 ,  H01L29/7923

摘要： A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

摘要翻译： 提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储单元。 单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P < SUP + +源极掺杂区域和P + +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。 氮化硅层用作电荷捕获层。

公开(公告)号：US20070109860A1

公开(公告)日：2007-05-17

申请号：US11277365

申请日：2006-03-24

申请人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Shih-Jye Shen ,  Ya-Chin King ,  Ching-Hsiang Hsu

发明人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Shih-Jye Shen ,  Ya-Chin King ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/6656 ,  H01L29/7881 ,  H01L29/7923

摘要： A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer include a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer. The metallurgical junction of P-type drain and N-type well locates underneath the ONO sidewall.

摘要翻译： 提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储单元。 单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P +源极 掺杂区域和P +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。 氮化硅层用作电荷捕获层。 P型漏极和N型阱的冶金结点位于ONO侧壁下方。

公开(公告)号：US20070108508A1

公开(公告)日：2007-05-17

申请号：US11277364

申请日：2006-03-24

申请人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Shih-Jye Shen ,  Ya-Chin King ,  Ching-Hsiang Hsu

发明人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Shih-Jye Shen ,  Ya-Chin King ,  Ching-Hsiang Hsu

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： G11C16/0475 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/6656 ,  H01L29/7881 ,  H01L29/7923

摘要： A single-poly, P-channel non-volatile memory (NVM) cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layers on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layers include a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer. The metallurgical junction of P-type drain and N-type well locates underneath the sidewall ONO layers.

摘要翻译： 提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储器（NVM）单元。 单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P < SUP + +源极掺杂区域和P + +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。 氮化硅层用作电荷捕获层。 P型漏极和N型阱的冶金结点位于侧壁ONO层的下方。

公开(公告)号：US20070058104A1

公开(公告)日：2007-03-15

申请号：US11518730

申请日：2006-09-11

申请人： Hsin-Ming Chen ,  Yu-Ju Hsu

发明人： Hsin-Ming Chen ,  Yu-Ju Hsu

IPC分类号： G02F1/1335

CPC分类号： G02F1/133606

摘要： An exemplary light guide plate (31) includes a light incident surface (310), a light output surface (312) adjacent to the light incident surface, and a bottom surface (313) opposite to the light output surface. The bottom surface includes a plurality of W-shaped structures (314) thereat. With such configuration, the output light beams can be concentrated to make the intensity distribution of the output light beams to be even. A backlight module employing the light guide plate is also provided.

公开(公告)号：US20070045716A1

公开(公告)日：2007-03-01

申请号：US11163716

申请日：2005-10-28

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L29/792 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/115

摘要： A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.

摘要翻译： 公开了包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一栅极结构和第二栅极结构的非易失性存储器。 掺杂区域设置在衬底中，第二掺杂区域设置在第一掺杂区域和第三掺杂区域之间。 第一栅极结构设置在第一掺杂区和第二掺杂区之间的衬底上。 第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的衬底上，并且包括隧道电介质层，电荷捕获结构和从下向上的栅极。

公开(公告)号：US07115431B2

公开(公告)日：2006-10-03

申请号：US10409453

申请日：2003-04-09

申请人： Hsin-Ming Chen

发明人： Hsin-Ming Chen

IPC分类号： H01L21/84

CPC分类号： G02F1/13454 ,  G02F1/133553 ,  G02F1/136213

摘要： A method of forming a liquid crystal display device with a pixel TFT, a bottom electrode of pixel capacitor CL, and a storage capacitor Cs in a pixel region, and an n-type TFT and a p-type TFT in a driving circuit region is disclosed. Firstly, a metal layer and an n-type silicon layer are formed on a transparent substrate. Thereafter, a patterning step is performed to define some predefined regions for above devices. After an active layer and a gate oxide layer are formed in order on all patterned surfaces, another patterning step is done to form a first, a second, and a third preserved region, respectively, for a LDD region of the n type TFT, source/drain regions for the p type TFT and a LDD region for pixel TFT and Cs. Thereafter, a photosensitive layer is deposited and patterned to form a reflective bumps region. A metal layer is formed and patterned to form a cover over the reflective bumps region and gate electrodes for aforementioned TFT as well as an upper electrode for Cs. Subsequently, a blanket nLDD implant is performed. Thereafter, a p type source/drain implant is carried out using a photoresist pattern as a mask. After removing the photoresist pattern, a passivation layer is formed on all areas. Next an annealing is performed to active the implant impurities. Another patterning process is then performed to expose the metal reflective layer over the bumps region and to form contact by patterning the passivation layer.

摘要翻译： 在像素区域中形成具有像素TFT，像素电容器CL的底电极和存储电容器Cs的液晶显示装置以及驱动电路区域中的n型TFT和p型TFT的方法是 披露 首先，在透明基板上形成金属层和n型硅层。 此后，执行图案化步骤以限定上述设备的一些预定区域。 在所有图案化表面上依次形成有源层和栅极氧化物层之后，进行另一图案化步骤以形成用于n型TFT的LDD区域的第一，第二和第三保留区域 /漏极区域和用于像素TFT和Cs的LDD区域。 此后，将感光层沉积并图案化以形成反射凸起区域。 形成金属层并图案化以在反射凸起区域上形成覆盖物，并在上述TFT上形成栅电极以及用于Cs的上电极。 随后，进行覆盖的nLDD植入。 此后，使用光致抗蚀剂图案作为掩模进行p型源极/漏极注入。 在去除光致抗蚀剂图案之后，在所有区域上形成钝化层。 接下来进行退火以使植入物的杂质起作用。 然后执行另一个图案化工艺以将凸起区域上的金属反射层暴露出来，并通过图案化钝化层形成接触。

公开(公告)号：US20060046374A1

公开(公告)日：2006-03-02

申请号：US10933120

申请日：2004-09-01

申请人： Hsin-Ming Chen ,  Wen-Yuan Guo ,  Jun-Chang Chen

发明人： Hsin-Ming Chen ,  Wen-Yuan Guo ,  Jun-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  H01L27/124 ,  H01L27/1248

摘要： A conducting line terminal structure for a display device. The conducting line terminal structure comprises a conducting member and an insulating layer covering a first section of the conductive member. A planarization layer is formed above a second section of the conductive member and overlaps a first section of the insulating layer and a conducting layer conductively couples to a third section of the conductive member.

摘要翻译： 一种用于显示装置的导线端子结构。 导线端子结构包括导电构件和覆盖导电构件的第一部分的绝缘层。 在导电部件的第二部分上方形成平坦化层，并且与绝缘层的第一部分重叠，并且导电层导电耦合到导电部件的第三部分。

公开(公告)号：US20050255623A1

公开(公告)日：2005-11-17

申请号：US10842553

申请日：2004-05-11

申请人： Hsin-Ming Chen

发明人： Hsin-Ming Chen

IPC分类号： G02F1/1335 ,  G02F1/1362 ,  H01L21/00 ,  H01L21/77 ,  H01L21/84

CPC分类号： H01L27/1288 ,  G02F1/133555 ,  G02F1/13454 ,  H01L27/1214

摘要： A conductive layer, a metal layer and a doped layer are sequentially formed on a glass substrate. A CMOS circuit region, a transistor region, a reflective region, a transmission region and a capacitor region are defined. Next, a polysilicon layer and an insulating layer are formed to serve as a source/drain region, a channel region and a gate insulating layer. Then, a resin layer with a rough surface is formed. Next, a metal layer is formed to serve as a gate structure and a reflective electrode. Then, an ion implanting process is performed to form the source/drain structure of a PMOS. Then, a passivation layer is formed to define a transmission region. Finally, the metal layer and the doped layer are removed to expose the conductive layer.

摘要翻译： 导电层，金属层和掺杂层依次形成在玻璃基板上。 定义CMOS电路区域，晶体管区域，反射区域，透射区域和电容器区域。 接下来，形成多晶硅层和绝缘层以用作源/漏区，沟道区和栅极绝缘层。 然后，形成具有粗糙表面的树脂层。 接下来，形成用作栅极结构和反射电极的金属层。 然后，执行离子注入工艺以形成PMOS的源极/漏极结构。 然后，形成钝化层以限定透射区域。 最后，去除金属层和掺杂层以暴露导电层。

公开(公告)号：US06812083B2

公开(公告)日：2004-11-02

申请号：US10463610

申请日：2003-06-18

申请人： Shih-Jye Shen ,  Wei-Zhe Wong ,  Ming-Chou Ho ,  Hsin-Ming Chen

发明人： Shih-Jye Shen ,  Wei-Zhe Wong ,  Ming-Chou Ho ,  Hsin-Ming Chen

IPC分类号： H01L21336

CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C2216/10

摘要： A fabrication method for a non-volatile memory includes providing a first metal oxide semiconductor (MOS) transistor having a control gate and a second MOS transistor having a source, a drain, and a floating gate. The first MOS transistor and the second MOS transistor are formed on a well. The method further includes biasing the first MOS with a first biasing voltage to actuate the first MOS transistor, biasing the second MOS transistor with a second biasing voltage to enable the second MOS transistor to generate a gate current, and adjusting capacitances between the floating gate of the second MOS transistor and the drain, the source, the control gate, and the well according to voltage difference between the floating gate of the second MOS transistor and the source of the second MOS transistor.

摘要翻译： 用于非易失性存储器的制造方法包括提供具有控制栅极的第一金属氧化物半导体（MOS）晶体管和具有源极，漏极和浮置栅极的第二MOS晶体管。 第一MOS晶体管和第二MOS晶体管形成在阱上。 该方法还包括以第一偏置电压偏置第一MOS以致动第一MOS晶体管，以第二偏置电压偏置第二MOS晶体管，以使第二MOS晶体管产生栅极电流，并调整第二MOS晶体管的浮置栅极之间的电容 第二MOS晶体管和漏极，源极，控制栅极和阱，根据第二MOS晶体管的浮置栅极和第二MOS晶体管的源极之间的电压差。

公开(公告)号：US06734055B1

公开(公告)日：2004-05-11

申请号：US10295157

申请日：2002-11-15

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Hsin-Ming Chen

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Hsin-Ming Chen

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7887

摘要： A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.

摘要翻译： 提供了一种用于形成具有多个浮动栅极的结构的高密度堆叠栅极快闪存储器单元的方法，该浮置栅极可以呈现4个状态，因此同时存储2个位。 这通过提供其上形成有栅极氧化物的半导体衬底和浅沟槽隔离以及其中形成的p阱来实现。 接着在衬底上形成一层氮化物，并在其中形成一个开口。 在开口中形成多晶硅浮栅隔板。 然后在浮动栅极上形成电介质层，随后形成控制栅极。 然后去除相邻的氮化物层，留下多层结构，其中包括在具有中间介电层的多个浮动栅之间的控制栅极。