公开(公告)号：US20130161588A1

公开(公告)日：2013-06-27

申请号：US13723149

申请日：2012-12-20

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U.LEUVEN R&D

Inventor： Geert Hellings ,  Geert Eneman

IPC: H01L29/775 ,  H01L29/66

CPC classification number: H01L29/7782 ,  H01L29/0623 ,  H01L29/36

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract translation: 一种无植入物量子阱晶体管，其中所述掺杂区域包括相对于所述衬底的相邻区域的掺杂剂的浓度具有增加的掺杂剂浓度的注入区域，所述注入区域基本上位于所述量子阱区域的相对侧 门区域。

公开(公告)号：US20230025767A1

公开(公告)日：2023-01-26

申请号：US17869289

申请日：2022-07-20

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Hellings ,  Geert Van der Plas

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/786

Abstract: An example includes a semiconductor structure including a semiconductor layer, front-side logic devices arranged in a front-side of the semiconductor layer, four epitaxial layers on a back-side of the semiconductor layer, where the four epitaxial layers include a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type, a third epitaxial layer of the second conductivity type, and a fourth epitaxial layer of the first conductivity type, a plurality of back-side contacts exposed at a back-side surface of the fourth epitaxial layer, where the plurality of back-side contacts include a set of first terminal contacts extending into and contacting the fourth epitaxial layer, a set of second terminal contacts extending into and contacting the second epitaxial layer, a set of first gate contacts extending into the third epitaxial layer, and a set of second gate contacts extending into the first epitaxial layer.

公开(公告)号：US20210159321A1

公开(公告)日：2021-05-27

申请号：US17099339

申请日：2020-11-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R & D

Inventor： Koen Martens ,  Sybren Santermans ,  Geert Hellings ,  David Barge

IPC: H01L29/66 ,  G01N27/414

Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

公开(公告)号：US10566434B2

公开(公告)日：2020-02-18

申请号：US15853136

申请日：2017-12-22

Applicant: IMEC VZW

Inventor： Geert Hellings

IPC: H01L29/423 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321

Abstract: The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer. The method additionally includes selectively etching to remove the first semiconductor material layer along a longitudinal section of the first semiconductor feature to form a suspended longitudinal first semiconductor feature of a remaining second semiconductor material layer, while masking the second region to prevent etching of the second semiconductor feature. The method additionally includes forming a gate-all-around electrode surrounding the suspended longitudinal first semiconductor feature in the first region. The method further includes forming a gate electrode on the fin-shaped second semiconductor feature in the second region.

公开(公告)号：US09391060B2

公开(公告)日：2016-07-12

申请号：US14581008

申请日：2014-12-23

Applicant: IMEC vzw

Inventor： Geert Hellings ,  Dimitri Linten

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0248 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: An electrostatic discharge (ESD) protection device implemented in finFET technology is disclosed. The device has a reduced thickness shallow trench isolation (STI) layer which allows migration of high-doped drain implants therethrough to form regions extending under the STI layer thereby creating a planar-like region under the STI layer. Further, the regions are formed in an n-well layer provided between a substrate and the STI layer. The formation of the planar-like region under the STI layer has the advantage that part of the thermal energy produced in the device during an ESD event is generated under the STI layer where it can be more efficiently dissipated towards a substrate.

Abstract translation: 公开了一种以finFET技术实现的静电放电（ESD）保护器件。 器件具有减小厚度的浅沟槽隔离（STI）层，其允许高掺杂漏极注入通过其迁移以形成在STI层下延伸的区域，从而在STI层下面形成平面状区域。 此外，这些区域形成在设置在基板和STI层之间的n阱层中。 STI层下方的平面状区域的形成具有以下优点：在ESD事件期间在器件中产生的热能的一部分在STI层下产生，其中可以更有效地朝向衬底散发。

公开(公告)号：US09159860B2

公开(公告)日：2015-10-13

申请号：US14087983

申请日：2013-11-22

Applicant: IMEC

Inventor： Geert Hellings ,  Joris Van Campenhout ,  Peter Verheyen

IPC: H01L31/0232 ,  H01L31/107 ,  H01L31/0224 ,  H01L31/028 ,  H01L31/0352

CPC classification number: H01L31/107 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/03529 ,  Y02E10/547

Abstract: An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array.

Abstract translation: 公开了一种用于将光信号转换成电信号的雪崩光电检测器元件，其包括输入波导和光电检测器区域，所述光电检测器区域包括至少一个本征区域，至少一个p掺杂区域和至少一个n掺杂区域 ，掺杂区域和至少一个本征区域形成至少一个PIN结雪崩光电二极管，输入波导和光电检测器区域相对于彼此布置，使得由输入波导传导的光信号基本上进入 光电检测器区域到PIN结雪崩光电二极管，PIN结雪崩光电二极管将光信号转换为电信号，其特征在于光电检测器区域包括多于一个p掺杂区域和/或n掺杂区域，由此这些p 掺杂区域和/或n掺杂区域物理地排列成阵列。

公开(公告)号：US20130181301A1

公开(公告)日：2013-07-18

申请号：US13725587

申请日：2012-12-21

Applicant: IMEC ,  Katholieke Universiteit Leuven

Inventor： Liesbeth Witters ,  Jerome Mitard ,  Geert Hellings

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess.

Abstract translation: 公开了制造半导体器件的方法。 一方面，该方法包括：在衬底层上形成虚拟栅极; 形成与所述虚拟栅极的侧壁相邻并且在所述衬底层上方的第一栅极绝缘间隔物，所述第一间隔物具有两个侧壁和两个表面轮廓，其中所述侧壁与所述衬底层相遇; 使用所述表面轮廓形成源极和漏极区域; 形成与所述第一间隔物的侧壁相邻并且在所述源极和漏极区域上的第二栅极绝缘间隔物; 去除所述伪栅极和所述第一间隔物，从而形成第一凹部; 在所述第一凹部中沿所述第二间隔物的侧壁和所述基底层上沉积介电层，由此形成第二凹槽; 以及在所述第二凹部中沉积栅电极。

公开(公告)号：US10469083B2

公开(公告)日：2019-11-05

申请号：US15644614

申请日：2017-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Erik Bury ,  Jacopo Franco ,  Geert Hellings ,  Robin Degraeve ,  Benjamin Kaczer

IPC: H03K19/003 ,  H01L21/326 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H04L9/14 ,  H01L23/00 ,  H04L9/08 ,  H04L9/32 ,  G09C1/00 ,  H03K17/00

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

公开(公告)号：US20170062431A1

公开(公告)日：2017-03-02

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

Abstract translation: 所公开的技术涉及半导体，更具体地涉及结型场效应晶体管（JFET）。 一方面，一种制造JFET的方法包括在衬底中形成第一掺杂剂阱，其中阱通过第二掺杂剂类型的隔离区与衬底隔离。 该方法另外包括在阱的表面处注入第二掺杂剂类型的掺杂剂以形成JFET的源极，漏极和沟道，以及在阱的表面处注入第一掺杂剂类型的掺杂剂，以形成 JFET栅极。 该方法还包括在植入第一类型的掺杂剂和第二类型的掺杂剂之前，在阱上形成预金属电介质（PMD）层并在源上形成PMD层中的接触开口，漏极和 大门。 PMD层的厚度使得通过PMD层注入第一类掺杂剂和第二类掺杂剂形成沟道。 该方法还包括在注入第一类型的掺杂剂和第二类型的掺杂剂之后，将源极，漏极和栅极硅化，并在接触开口中形成金属接触。

公开(公告)号：US09263401B2

公开(公告)日：2016-02-16

申请号：US14066545

申请日：2013-10-29

Applicant: IMEC

Inventor： Geert Hellings ,  Mirko Scholz ,  Dimitri Linten

IPC: H01L23/60 ,  H01L29/36 ,  H01L29/66 ,  H01L29/866 ,  H01L29/73 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L23/60 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/6609 ,  H01L29/66098 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/7302 ,  H01L29/735 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction.

Abstract translation: 所公开的技术涉及包括不同掺杂类型的两个半导体区域之间的二极管结的半导体器件。 在一个方面，二极管包括在有源区的上部和有源区的其余部分之间形成的结，其中有源区限定在两个场介电区之间的衬底中。 上部是活动区域的宽度小于有效区域本身的宽度的部分。 在另一方面，半导体器件是包括这种二极管的静电放电保护器件（ESD）。 此外，有源区具有在有源区的表面处呈现最大值的掺杂分布，并且在第一深度处变化为最小值，其中第一深度可以比值的深度的一半更大 上部。 在另一方面，制造该器件的方法不需要用于降低保持电压的单独的ESD注入，并且可以允许减少处理步骤的数量以及包括二极管结的其它器件。