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    Logic gates based on phase shifters
    11.
    发明授权
    Logic gates based on phase shifters 有权

    公开(公告)号：US12125623B2

    公开(公告)日：2024-10-22

    申请号：US17804550

    申请日：2022-05-27

    Applicant: IMEC VZW

    Inventor： Florin Ciubotaru ,  Hanns Christoph Adelmann

    IPC: H01F10/32 ,  H01P1/18 ,  H03K19/21

    CPC classification number: H01F10/32 ,  H01P1/18 ,  H03K19/21

    Abstract: The disclosed technology relates to a logic device based on spin waves. In one aspect, the logic device includes a spin wave generator, a waveguide, at least two phase shifters, and an output port. The spin wave generator is connected with the waveguide and is configured to emit a spin wave in the waveguide. The at least two phase shifters are connected with the waveguide at separate positions such that, when a spin wave is emitted by the spin wave generator, it passes via the phase shifters. The at least two phase shifters are configured to change a phase of the passing spin wave. The output port is connected with the wave guide such that the at least two phase shifters are present between the spin wave generator and the output port.

    Method of fabricating ferroelectric field-effect transistor
    13.
    发明授权
    Method of fabricating ferroelectric field-effect transistor 审中-公开

    公开(公告)号：US10672894B2

    公开(公告)日：2020-06-02

    申请号：US16216833

    申请日：2018-12-11

    Applicant: IMEC vzw

    Inventor： Jan Van Houdt ,  Hanns Christoph Adelmann ,  Han Chung Lin

    IPC: H01L29/66 ,  H01L29/51 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02

    Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

    METHOD OF FABRICATING FERROELECTRIC FIELD-EFFECT TRANSISTOR
    14.
    发明申请
    METHOD OF FABRICATING FERROELECTRIC FIELD-EFFECT TRANSISTOR 审中-公开

    公开(公告)号：US20190198638A1

    公开(公告)日：2019-06-27

    申请号：US16216833

    申请日：2018-12-11

    Applicant: IMEC vzw

    Inventor： Jan Van Houdt ,  Hanns Christoph Adelmann ,  Han Chung Lin

    IPC: H01L29/66 ,  H01L21/02

    Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

    WAVE-BASED MAJORITY GATE DEVICE
    15.
    发明申请
    WAVE-BASED MAJORITY GATE DEVICE 审中-公开

    公开(公告)号：US20180175863A1

    公开(公告)日：2018-06-21

    申请号：US15849372

    申请日：2017-12-20

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Odysseas Zografos ,  Bart Soree ,  Florin Ciubotaru ,  Hanns Christoph Adelmann

    IPC: H03K19/23 ,  H03K19/168 ,  G06F1/04

    CPC classification number: H03K19/23 ,  G01R33/1284 ,  G01R33/18 ,  G06F1/04 ,  H03K19/168

    Abstract: The disclosed technology generally relates to computation devices, and more particularly to majority gate devices configured for computation based on spin waves. In one aspect, a majority gate device comprises cells that are configurable as spin wave generators or spin wave detectors. The majority gate device comprises an odd number of spin wave generators, and at least one spin wave detector. The majority gate device additionally comprises a waveguide adapted for guiding spin waves generated by the spin wave generators. The spin wave generators and the at least one spin wave detector are positioned in an inline configuration along the waveguide such that, in operation, interference of the spin waves generated by the spin wave generators can be detected by the at least one spin wave detector. The interference of the spin waves corresponds to a majority operation of the spin waves generated by the spin wave generators.

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