公开(公告)号：US20190043598A1

公开(公告)日：2019-02-07

申请号：US16155158

申请日：2018-10-09

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Adrien Vaysset ,  Odysseas Zografos

IPC: G11C19/08 ,  G11C11/16

CPC classification number: G11C19/0841 ,  G11C5/063 ,  G11C11/1673 ,  G11C11/1675

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include at least a first magnetic bus, a second magnetic bus, and an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. In another aspect, a method includes providing the magnetic device and generating the stream of domain walls propagating along the output magnetic bus.

公开(公告)号：US10802743B2

公开(公告)日：2020-10-13

申请号：US16028328

申请日：2018-07-05

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Daniele Garbin ,  Dimitrios Rodopoulos ,  Odysseas Zografos

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C7/10 ,  G06N3/063 ,  G11C17/16 ,  G11C11/54 ,  G06N3/04 ,  G06N3/08

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

公开(公告)号：US20190064438A1

公开(公告)日：2019-02-28

申请号：US16100016

申请日：2018-08-09

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Odysseas Zografos ,  Francky Catthoor ,  Sourav Dutta ,  Azad Naeemi

IPC: G02B6/122 ,  G02B5/00 ,  G01N21/552

CPC classification number: G02B6/1226 ,  B82Y20/00 ,  G01N21/554 ,  G02B5/008 ,  G02B6/125

Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over π with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.

公开(公告)号：US10593414B2

公开(公告)日：2020-03-17

申请号：US16155158

申请日：2018-10-09

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Adrien Vaysset ,  Odysseas Zografos

IPC: G11C11/16 ,  G11C19/08 ,  G11C5/06

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include at least a first magnetic bus, a second magnetic bus, and an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. In another aspect, a method includes providing the magnetic device and generating the stream of domain walls propagating along the output magnetic bus.

公开(公告)号：US20180175863A1

公开(公告)日：2018-06-21

申请号：US15849372

申请日：2017-12-20

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Odysseas Zografos ,  Bart Soree ,  Florin Ciubotaru ,  Hanns Christoph Adelmann

IPC: H03K19/23 ,  H03K19/168 ,  G06F1/04

CPC classification number: H03K19/23 ,  G01R33/1284 ,  G01R33/18 ,  G06F1/04 ,  H03K19/168

Abstract: The disclosed technology generally relates to computation devices, and more particularly to majority gate devices configured for computation based on spin waves. In one aspect, a majority gate device comprises cells that are configurable as spin wave generators or spin wave detectors. The majority gate device comprises an odd number of spin wave generators, and at least one spin wave detector. The majority gate device additionally comprises a waveguide adapted for guiding spin waves generated by the spin wave generators. The spin wave generators and the at least one spin wave detector are positioned in an inline configuration along the waveguide such that, in operation, interference of the spin waves generated by the spin wave generators can be detected by the at least one spin wave detector. The interference of the spin waves corresponds to a majority operation of the spin waves generated by the spin wave generators.

公开(公告)号：US10439616B2

公开(公告)日：2019-10-08

申请号：US15849372

申请日：2017-12-20

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Odysseas Zografos ,  Bart Soree ,  Florin Ciubotaru ,  Hanns Christoph Adelmann

IPC: H03K19/23 ,  G06F1/04 ,  H03K19/168 ,  G01R33/12 ,  G01R33/18

Abstract: The disclosed technology generally relates to computation devices, and more particularly to majority gate devices configured for computation based on spin waves. In one aspect, a majority gate device comprises cells that are configurable as spin wave generators or spin wave detectors. The majority gate device comprises an odd number of spin wave generators, and at least one spin wave detector. The majority gate device additionally comprises a waveguide adapted for guiding spin waves generated by the spin wave generators. The spin wave generators and the at least one spin wave detector are positioned in an inline configuration along the waveguide such that, in operation, interference of the spin waves generated by the spin wave generators can be detected by the at least one spin wave detector. The interference of the spin waves corresponds to a majority operation of the spin waves generated by the spin wave generators.

公开(公告)号：US20180175193A1

公开(公告)日：2018-06-21

申请号：US15835703

申请日：2017-12-08

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Praveen Raghavan ,  Odysseas Zografos

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/66666 ,  H01L29/7831

Abstract: A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.

公开(公告)号：US10732350B2

公开(公告)日：2020-08-04

申请号：US16100016

申请日：2018-08-09

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Odysseas Zografos ,  Francky Catthoor ,  Sourav Dutta ,  Azad Naeemi

IPC: G02B6/10 ,  G02B6/122 ,  G01N21/552 ,  G02B5/00 ,  G02B6/125 ,  B82Y20/00

Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over π with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.

公开(公告)号：US10355128B2

公开(公告)日：2019-07-16

申请号：US15835703

申请日：2017-12-08

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Praveen Raghavan ,  Odysseas Zografos

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.

公开(公告)号：US20190034111A1

公开(公告)日：2019-01-31

申请号：US16028328

申请日：2018-07-05

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Daniele Garbin ,  Dimitrios Rodopoulos ,  Odysseas Zografos

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0646 ,  G06F3/0604 ,  G06F3/0673 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/088 ,  G11C7/1006 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0061 ,  G11C16/04 ,  G11C17/165 ,  G11C2213/71

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.