公开(公告)号：US11721689B2

公开(公告)日：2023-08-08

申请号：US17878990

申请日：2022-08-02

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Thomas Basler ,  Philip Christoph Brandt ,  Maria Cotorogea

IPC: H01L27/02 ,  H01L29/40 ,  H01L29/861 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H03K17/082

CPC classification number: H01L27/0266 ,  H01L27/0255 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8613 ,  H03K17/0828

Abstract: A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction. The semiconductor auxiliary region is positioned closest to the semiconductor channel region as compared to any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

公开(公告)号：US10680089B2

公开(公告)日：2020-06-09

申请号：US16456895

申请日：2019-06-28

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.

公开(公告)号：US10424645B2

公开(公告)日：2019-09-24

申请号：US15657735

申请日：2017-07-24

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Erich Griebl ,  Johannes Georg Laven ,  Maria Cotorogea

IPC: H01L23/58 ,  H01L21/66 ,  H01L29/40 ,  H01L29/66 ,  H01L21/786 ,  H01L29/417 ,  H01L21/8234 ,  G01R31/02 ,  G01R31/26 ,  H01L23/522 ,  H01L29/739 ,  H01L29/78

Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

公开(公告)号：US20150041962A1

公开(公告)日：2015-02-12

申请号：US13963312

申请日：2013-08-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/22

CPC classification number: H01L29/06 ,  H01L21/22 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/31111 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract translation: 第一和第二单元沟槽结构从第一表面延伸到半导体衬底。 第一单元沟槽结构包括第一掩埋电极和第一绝缘体层之间的第一掩埋电极和分隔第一和第二单元沟道结构的半导体台面之间的第一绝缘体层。 覆盖层覆盖第一表面。 将覆盖层图案化以形成具有大于第一绝缘体层的厚度的最小宽度的开口。 开口在第一表面暴露第一绝缘体层的第一垂直截面。 去除第一绝缘体层的暴露部分以在半导体台面和第一掩埋电极之间形成凹部。 接触结构位于开口和凹部中。 接触结构电连接半导体台面中的掩埋区和第一掩埋电极，并允许较窄的半导体台面宽度。

公开(公告)号：US20140264432A1

公开(公告)日：2014-09-18

申请号：US13796287

申请日：2013-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.

Abstract translation: 半导体衬底中的半导体器件包括第一主表面和晶体管单元。 晶体管单元包括第一导电类型的漂移区域，漂移区域和第一主表面之间的第二导电类型的体区域，延伸到漂移区域的第一主表面中的有源沟槽，源极区域 在与主动沟槽相邻的主体区域中的第一导电性，以及在第一主表面处延伸到漂移区并且与身体区域和漂移区域相邻的主体沟槽。 有源沟槽包括在侧壁和底侧的栅极绝缘层和栅极导电层。 主体沟槽包括在侧壁和底侧的导电层和绝缘层，并且与第一主表面和体沟槽中心的垂直轴不对称。

公开(公告)号：US20200295168A1

公开(公告)日：2020-09-17

申请号：US16890822

申请日：2020-06-02

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.

公开(公告)号：US20190103480A1

公开(公告)日：2019-04-04

申请号：US16189279

申请日：2018-11-13

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.

公开(公告)号：US10134885B2

公开(公告)日：2018-11-20

申请号：US15594269

申请日：2017-05-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

公开(公告)号：US20170243969A1

公开(公告)日：2017-08-24

申请号：US15589531

申请日：2017-05-08

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L21/311 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/06 ,  H01L21/22 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/31111 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

公开(公告)号：US09711641B2

公开(公告)日：2017-07-18

申请号：US15188217

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/40 ,  H01L29/08 ,  H01L29/739

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811

Abstract: A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.