公开(公告)号：US20190043567A1

公开(公告)日：2019-02-07

申请号：US16115372

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Shantanu Rajwade ,  Rohit Shenoy ,  Aliasgar Madraswala ,  Pranav Kalavade

IPC: G11C11/56 ,  G11C16/26 ,  H01L23/00 ,  G06F3/06

Abstract: An apparatus and/or system is described including a memory device or a controller for a memory device to perform an adjustment of a read operation time for data stored in the memory device. In embodiments, the apparatus may receive a request for data stored in the memory device and a read operation time adjustment module operable by the controller may acquire a first operation temperature of the memory device, obtained at a time of programming of the data stored in the memory device. The apparatus may acquire a second operation temperature of the memory device, obtained after the request for the data stored in the memory device is received. Based at least partially on the first operation temperature and the second operation temperature, the apparatus may adjust the read operation time to read the data. Other embodiments are disclosed and claimed.

公开(公告)号：US10109361B1

公开(公告)日：2018-10-23

申请号：US15637481

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Aliasgar S. Madraswala ,  Donia Sebastian ,  Xin Guo

IPC: G11C16/04 ,  G11C16/34

Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

公开(公告)号：US12224015B2

公开(公告)日：2025-02-11

申请号：US17236651

申请日：2021-04-21

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Rezaul Haque ,  Dhanashree Kulkarni ,  Bayan Nasri

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.

公开(公告)号：US20220343982A1

公开(公告)日：2022-10-27

申请号：US17236651

申请日：2021-04-21

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Rezaul Haque ,  Dhanashree Kulkarni ,  Bayan Nasri

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.

公开(公告)号：US11275245B2

公开(公告)日：2022-03-15

申请号：US16473983

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Ali Khakifirooz

IPC: G02B27/01 ,  H01L27/15 ,  H01L27/32 ,  H01L21/02 ,  H01L33/00 ,  G09G3/32 ,  H01L33/62 ,  H01L25/075

Abstract: Embodiments of the present disclosure describe light emitting displays having a light emitter layer that includes an array of light emitters and a wafer having a driving circuit coupled with the light emitter layer, computing devices incorporating the light emitting displays, methods for formation of the light emitting displays, and associated configurations. A light emitting display may include a light emitter layer that includes an array of light emitters and a wafer coupled with the light emitter layer, where the wafer includes a driving circuit formed thereon to drive the light emitters. Other embodiments may be described and/or claimed.

公开(公告)号：US10361337B2

公开(公告)日：2019-07-23

申请号：US15681234

申请日：2017-08-18

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  Ali Khakifirooz

IPC: H01L33/00

Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, method of manufacturing a micro-light emitting diode (LED) display panel includes positioning a display backplane substrate in a tank or container, the display backplane substrate having microgrooves therein. The method also includes adding a fluid to the tank or container, the fluid including a suspension of light-emitting diode (LED) pixel elements therein. The method also includes moving the fluid over the display backplane substrate. The method also includes assembling LED pixel elements from the fluid into corresponding ones of the microgrooves.

公开(公告)号：US10186676B2

公开(公告)日：2019-01-22

申请号：US15918893

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Ali Khakifirooz ,  Richmond Hicks

IPC: H01L27/32 ,  H01L51/50 ,  H01L51/56 ,  G02B6/27 ,  G02B6/35 ,  G02B27/10 ,  G06F3/01 ,  H01S5/183 ,  H01L33/24 ,  G02B27/01

Abstract: Embodiments related to emissive devices for displays are discussed. Some embodiments include light emitting diodes including an electron transport layer core having a tube shape with an inner and an outer sidewall, an emission layer on the inner and outer sidewalls, and a hole transport layer on the emission layer, displays and systems including such light emitting diodes, and methods for fabricating them. Other embodiments include emissive laser devices having an emission layer between a hole transport layer and an electron transport layer and first and second metasurface mirrors adjacent to the hole transport layer and the electron transport layer, respectively, displays and systems including such emissive laser devices, and methods for fabricating them.

公开(公告)号：US11693582B2

公开(公告)日：2023-07-04

申请号：US16947592

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Ali Khakifirooz ,  Camila Jaramillo ,  John Egler ,  Netra Mahuli ,  Renjie Chen ,  Yogesh Wakchaure

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26

Abstract: An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.

公开(公告)号：US11610936B2

公开(公告)日：2023-03-21

申请号：US16440755

申请日：2019-06-13

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  Ali Khakifirooz

IPC: H01L27/15 ,  H01L33/32 ,  H01L33/50 ,  G09F9/33 ,  H01L33/22

Abstract: Micro light-emitting diode displays and methods of fabricating micro LED displays are described. In an example, a micro light emitting diode pixel structure includes a plurality of micro light emitting diode devices in a dielectric layer. A transparent conducting oxide layer is above the dielectric layer. A color conversion device (CCD) is above the transparent conducting oxide layer and over one of the plurality of micro light emitting diode devices.

公开(公告)号：US20220310178A1

公开(公告)日：2022-09-29

申请号：US17213150

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/10

Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.